# US 8,786,097 B2 · Method of forming vias in semiconductor substrates and resulting structures

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- Number: US 8,786,097 B2
- Document ID: US8786097B2
- Status: Granted
- Kind: B2
- Application number: 12/955,359
- Filed: 2010-11-29
- Published: 2011-03-31
- Granted: 2014-07-22
- Earliest claimed: 2004-08-24
- Assignees: Micron Technology, Inc.
- Applicants: Charles M. Watkins; Kyle K. Kirby; Alan G. Wood; Salman Akram; Warren M. Farnworth
- Inventors: Charles M. Watkins; Kyle K. Kirby; Alan G. Wood; Salman Akram; Warren M. Farnworth
- Web page: https://patentgrep.com/patent/US8786097B2

## CPC

- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/2125: {Top-view shapes}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from a back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.

## Claims

### Claim 1

A semiconductor substrate having at least one through via formed therein, comprising:
a semiconductor substrate having at least one active region, an active surface including a plurality of discrete conductive elements thereon, and a back surface, wherein at least one discrete conductive element of the plurality of discrete conductive elements is located on a portion of the active surface without integrated circuitry under the at least one discrete conductive element; and
at least one through via extending from the active surface to the back surface at the portion of the active surface without integrated circuitry, wherein the at least one through via includes:
a first portion that extends from the active surface of the semiconductor substrate to at least a depth of the at least one active region; and
a second portion having a tapered cross-section that extends from the back surface of the semiconductor substrate to the first portion.

### Claim 2 (depends on 1)

The semiconductor substrate of claim 1, wherein the at least one through via further comprises an aperture formed through the at least one discrete conductive element and a dielectric material formed over the active surface.

### Claim 3 (depends on 1)

The semiconductor substrate of claim 1, wherein the first portion of the at least one through via extends from the active surface below the depth of the at least one active region.

### Claim 4 (depends on 1)

The semiconductor substrate of claim 1, wherein the first portion of the at least one through via extends beneath the active surface to a depth of between about 5 μm and about 20 μm.

### Claim 5 (depends on 1)

The semiconductor substrate of claim 1, wherein the first portion of the at least one through via exhibits a substantially frustoconical cross-section, a diameter of the first portion decreasing in a direction from the active surface toward the back surface.

### Claim 6 (depends on 1)

The semiconductor substrate of claim 1, wherein the first portion of the at least one through via exhibits a substantially uniform transverse cross-section.

### Claim 7

A semiconductor substrate, comprising:
a semiconductor device comprising an active region, an active surface including a plurality of discrete conductive elements thereon, and an opposing back surface, wherein at least one discrete conductive element of the plurality of discrete conductive elements is located on a portion of the active surface without integrated circuitry under the at least one discrete conductive element; and
at least one via extending through the semiconductor device comprising:
a first section extending through the active region at least to a depth of the active region, wherein a diameter of the first section decreases continuously from the active region to a terminus of the first section; and
a second section having a tapered cross-section extending from the back surface to the first section, wherein the second section tapers continuously from the back surface to the first section.

### Claim 8 (depends on 7)

The semiconductor substrate of claim 7, wherein the first section of the at least one via extends through the active region into a portion of the semiconductor device below the depth of the at least one active region.

### Claim 9 (depends on 7)

The semiconductor substrate of claim 7, wherein the first section comprises a substantially frustoconical cross-section.

### Claim 10 (depends on 7)

The semiconductor substrate of claim 7, wherein a diameter of the second section decreases in a direction from the back surface toward the active region.

### Claim 11 (depends on 7)

The semiconductor substrate of claim 7, further comprising: a dielectric material disposed over the active region; and wherein the at least one discrete conductive element of the plurality of discrete conductive elements is disposed over the dielectric material.

### Claim 12 (depends on 11)

The semiconductor substrate of claim 11, wherein the first section extends through the dielectric material.

### Claim 13 (depends on 12)

The semiconductor substrate of claim 12, wherein the first section extends through the at least one discrete conductive element.

### Claim 14 (depends on 11)

The semiconductor substrate of claim 11, further comprising:
a passivation material disposed over at least a portion of the dielectric material and at least a portion of the at least one discrete conductive element.

### Claim 15 (depends on 7)

The semiconductor substrate of claim 7, wherein the at least one via is at least substantially filled with a conductive filler material.

### Claim 16 (depends on 15)

The semiconductor substrate of claim 15, wherein side walls of the at least one via are coated with dielectric material.

### Claim 17 (depends on 15)

The semiconductor substrate of claim 15, further comprising:
a redistribution layer comprising traces located on the back surface of the substrate.

### Claim 18 (depends on 17)

The semiconductor substrate of claim 17, further comprising:
discrete external conductive elements located on the redistribution layer.