# US 8,786,094 B2 · Semiconductor devices and methods of manufacture thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,094 B2 - Document ID: US8786094B2 - Status: Granted - Kind: B2 - Application number: 13/540,464 - Filed: 2012-07-02 - Published: 2014-01-02 - Granted: 2014-07-22 - Earliest claimed: 2012-07-02 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Chung-Min Fu; Wen-Hao Chen; Dian-Hau Chen - Inventors: Chung-Min Fu; Wen-Hao Chen; Dian-Hau Chen - Web page: https://patentgrep.com/patent/US8786094B2 ## CPC - H10W 20/01: {Manufacture or treatment} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 20/427: {Power or ground buses} - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality of second conductive lines comprises a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines. ## Claims ### Claim 1 A semiconductor device, comprising: a workpiece; a plurality of first conductive lines disposed over the workpiece in a metallization layer; a plurality of second conductive lines disposed over the workpiece in the metallization layer, wherein the plurality of second conductive lines comprise a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines; and wherein the plurality of first conductive lines comprise a first horizontal width in the cross-sectional view of the workpiece, wherein the plurality of second conductive lines comprise a second horizontal width in the cross-sectional view of the workpiece, and wherein the second horizontal width is less than the first horizontal width. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein one of the plurality of second conductive lines is disposed between two of the plurality of first conductive lines. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the second conductive lines are located at edges of the semiconductor device or at edges of a region of the semiconductor device and the first conductive lines are located in central regions between the second conductive lines, or wherein the first conductive lines are located at edges of the semiconductor device or at edges of a region of the semiconductor device and the second conductive lines are located in central regions between the first conductive lines. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of second conductive lines comprises power rails. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of first conductive lines comprises conductive lines for standard cells. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the second horizontal width is about one-third to one-half of the first horizontal width. ### Claim 7 A semiconductor device, comprising: a workpiece; a plurality of first conductive lines disposed over the workpiece in a metallization layer, the plurality of first conductive lines comprising a first vertical height in a cross-sectional view of the workpiece; a plurality of second conductive lines disposed over the workpiece in the metallization layer, the plurality of second conductive lines comprising a second vertical height in the cross-sectional view of the workpiece, wherein the second vertical height is greater than the first vertical height; and wherein the metallization layer comprises a first metallization layer, wherein a portion of the plurality of second conductive lines is disposed in a second metallization layer adjacent the first metallization layer, the second metallization layer being vertically above or vertically below the first metallization layer. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the second vertical height is about 1.5 to 3 times greater than the first vertical height. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, wherein the plurality of second conductive lines comprise a lower resistance than the plurality of first conductive lines. ### Claim 10 (depends on 7) The semiconductor device according to claim 7, wherein the plurality of first conductive lines and the plurality of second conductive lines are disposed within an insulating material. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the insulating material includes an etch stop layer formed therein, wherein a bottom surface of the plurality of second conductive lines is adjacent a top surface of the etch stop layer. ### Claim 12 A semiconductor device, comprising: a substrate; a dielectric layer on a major surface of the substrate; a plurality of first conductive lines disposed within the dielectric layer, the plurality of first conductive lines having a first thickness in a direction perpendicular to the major surface; a plurality of second conductive lines disposed within the dielectric layer and on a same horizontal plane, relative the major surface, as the plurality of first conductive lines, the plurality of second conductive lines having a second thickness in the direction perpendicular to the major surface, the second thickness being greater than the first thickness; and wherein the plurality of first conductive lines comprise a first horizontal width in a cross-sectional view of the workpiece, wherein the plurality of second conductive lines comprise a second horizontal width in the cross-sectional view of the workpiece, and wherein the second horizontal width is less than the first horizontal width. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the substrate is selected from the group consisting of silicon, silicon-on-insulator, germanium-on-insulator, and a compound semiconductor. ### Claim 14 (depends on 12) The semiconductor device according to claim 12, wherein one of the plurality of first conductive lines and the plurality of second conductive lines is located at edges of the semiconductor device or at edges of a region of the semiconductor device and the other of the plurality of first conductive lines and plurality of second conductive lines is located in a central region within the edges of the semiconductor device or region. ### Claim 15 (depends on 12) The semiconductor device according to claim 12, wherein the plurality of second conductive lines comprises power rails, and the plurality of first conductive lines comprises conductive lines for standard cells. ### Claim 16 (depends on 12) The semiconductor device according to claim 12, wherein the plurality of first conductive lines comprises a barrier layer and a conductor layer. ### Claim 17 (depends on 12) The semiconductor device according to claim 12, wherein the dielectric layer includes an etch stop layer, and wherein a bottom surface of the plurality of second conductive lines is adjacent a top surface of the etch stop layer. ### Claim 18 (depends on 1) The semiconductor device of claim 1, wherein each one of the plurality of first conductive lines comprises a first area in the cross-sectional view of the workpiece, each one of the second conductive lines has a second area in the cross-section view of the workpiece, and wherein the first area is equal to the second area. ### Claim 19 (depends on 7) The semiconductor device of claim 7, wherein the plurality of first conductive lines comprise a first horizontal width in the cross-sectional view of the workpiece, wherein the plurality of second conductive lines comprise a second horizontal width in the cross-sectional view of the workpiece, and wherein the second horizontal width is less than the first horizontal width. ### Claim 20 (depends on 12) The semiconductor device of claim 12 wherein each one of the plurality of first conductive lines comprises a first area in the cross-sectional view of the workpiece, each one of the second conductive lines has a second area in the cross-section view of the workpiece, and wherein the first area is equal to the second area.