# US 8,786,093 B2 · Chip package and method for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,093 B2 - Document ID: US8786093B2 - Status: Granted - Kind: B2 - Application number: 13/359,452 - Filed: 2012-01-26 - Published: 2012-08-02 - Granted: 2014-07-22 - Earliest claimed: 2011-01-27 - Applicants: Chia-Sheng Lin; Tzu-Hsiang Hung - Inventors: Chia-Sheng Lin; Tzu-Hsiang Hung - Web page: https://patentgrep.com/patent/US8786093B2 ## CPC - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/2125: {Top-view shapes} - H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 74/131: {the semiconductor body being only partially enclosed} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/654: Top-view layouts - H10W 70/656: Fan-in layouts - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/922: {Bond pads being integral with underlying chip-level interconnections} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An embodiment of the invention provides a chip package which includes: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; and a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers the entire side terminals of the signal conducting layer and partially covers the ground conducting layer such that a side terminal of the ground conducting layer is exposed on a side of the substrate. ## Claims ### Claim 1 A chip package, comprising: a substrate; a device region disposed in or on the substrate; a signal pad disposed in or on the substrate and electrically connected to the device region; a ground pad disposed in or on the substrate; a signal bump disposed on a surface of the substrate, wherein the signal bump is electrically connected to the signal pad through a signal conducting layer; a ground conducting layer disposed on the surface of the substrate and electrically connected to the ground pad; a protection layer disposed on the surface of the substrate, wherein the protection layer completely covers entire side edges of the signal conducting layer and partially covers the ground conducting layer such that a side edge of the ground conducting layer is exposed at a side of the substrate; a dummy electrical connection structure disposed on the surface of the substrate; and a conducting layer electrically connected to the dummy electrical connection structure, wherein the protection layer partially covers the conducting layer such that a side edge of the conducting layer is exposed. ### Claim 2 (depends on 1) The chip package as claimed in claim 1, further comprising a ground bump disposed on the surface of the substrate, wherein the ground bump is electrically connected to the ground conducting layer. ### Claim 3 (depends on 1) The chip package as claimed in claim 1, wherein the exposed side edge of the ground conducting layer is substantially coplanar with the side of the substrate. ### Claim 4 (depends on 1) The chip package as claimed in claim 1, further comprising a hole extending from the surface of the substrate towards the signal pad and exposing a portion of the signal pad, wherein the signal conducting layer extends from the surface of the substrate into the hole and electrically contacts with the signal pad. ### Claim 5 (depends on 1) The chip package as claimed in claim 1, further comprising a second hole extending from the surface of the substrate towards the ground pad of the substrate and exposing a portion of the ground pad, wherein the ground conducting layer extends from the surface of the substrate into the second hole and electrically contacts with the ground pad. ### Claim 6 (depends on 1) The chip package as claimed in claim 1, wherein the conducting layer is electrically connected to the ground conducting layer. ### Claim 7 (depends on 1) The chip package as claimed in claim 1, wherein the side edge of the conducting layer is exposed at a second side of the substrate. ### Claim 8 (depends on 1) The chip package as claimed in claim 1, further comprising a second ground conducting layer disposed on the surface of the substrate, wherein the protection layer partially covers the second ground conducting layer such that a side edge of the second ground conducting layer is exposed at a side of the substrate, and the second ground conducting layer is electrically connected to the ground conducting layer. ### Claim 9 (depends on 1) The chip package as claimed in claim 1, further comprising a shell covering the substrate, wherein the shell comprises a conducting portion electrically contacting with the ground conducting layer. ### Claim 10 (depends on 1) The chip package as claimed in claim 1, wherein the dummy electrical connection structure comprises a dummy bump. ### Claim 11 A method for forming a chip package, comprising: providing a substrate, wherein a device region, a signal pad, and a ground pad are respectively disposed in or on the substrate, and the signal pad is electrically connected to the device region; forming a signal conducting layer and a ground conducting layer on a surface of the substrate, wherein the signal conducting layer is electrically connected to the signal pad; forming a protection layer on the surface of the substrate, wherein the protection layer exposes a portion of the signal conducting layer and completely covers the entire side edges of the signal conducting layer, wherein a side edge of the ground conducting layer is exposed; forming a signal bump on the opening of the protection layer, wherein the signal bump is electrically connected to the signal pad through the signal conducting layer; disposing a dummy electrical connection structure on the surface of the substrate; forming a conducting layer on the substrate, wherein the conducting layer is electrically connected to the dummy electrical connection structure, and the protection layer partially covers the conducting layer such that a side edge of the conducting layer is exposed; and dicing the substrate to form at least one chip package, wherein the side edge of the ground conducting layer is exposed at a side of the substrate after the substrate is diced. ### Claim 12 (depends on 11) The method for forming a chip package as claimed in claim 11, further comprising: forming a second opening in the protection layer to expose a portion of the ground conducting layer; and forming a ground bump on the second opening. ### Claim 13 (depends on 11) The method for forming a chip package as claimed in claim 11, wherein after the step of dicing the substrate is performed, the exposed side edge of the ground conducting layer is substantially coplanar with a side of the substrate. ### Claim 14 (depends on 11) The method for forming a chip package as claimed in claim 11, further comprising: before the signal conducting layer is formed, removing a portion of the substrate from a second surface of the substrate to form a hole extending towards the signal pad, wherein the hole exposes the signal pad; forming a conducting material layer on the surface of the substrate, wherein the conducting material layer extends into the hole to electrically contact with the signal pad; and patterning the conducting material layer to form the signal conducting layer. ### Claim 15 (depends on 11) The method for forming a chip package as claimed in claim 11, further comprising: before the ground conducting layer is formed, removing a portion of the substrate from a second surface of the substrate to form a second hole extending towards the ground pad, wherein the second hole exposes the ground pad; forming a conducting material layer on the surface of the substrate, wherein the conducting material layer extends into the second hole to electrically contact with the ground pad; and patterning the conducting material layer to form the ground conducting layer. ### Claim 16 (depends on 11) The method for forming a chip package as claimed in claim 11, wherein the formation steps of forming the signal conducting layer and the ground conducting layer comprise: forming a conducting material layer on the surface of the substrate; and patterning the conducting material layer to simultaneously form the signal conducting layer and the ground conducting layer. ### Claim 17 (depends on 11) The method for forming a chip package as claimed in claim 11, wherein the conducting layer is electrically connected to the ground conducting layer. ### Claim 18 (depends on 11) The method for forming a chip package as claimed in claim 11, wherein the signal conducting layer, the ground conducting layer, and the conducting layer are patterned from a same conducting material layer. ### Claim 19 (depends on 11) The method for forming a chip package as claimed in claim 11, further comprising covering the at least one chip package by a shell, wherein the shell comprises a conducting portion electrically contacting with the ground conducting layer. ### Claim 20 (depends on 11) The method for forming a chip package as claimed in claim 11, wherein the dummy electrical connection structure comprises a dummy bump.