# US 8,786,092 B2 · Semiconductor integrated circuit device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,092 B2 - Document ID: US8786092B2 - Status: Granted - Kind: B2 - Application number: 13/240,054 - Filed: 2011-09-22 - Published: 2012-09-27 - Granted: 2014-07-22 - Earliest claimed: 2005-06-17 - Assignees: Rohm Co., Ltd. - Applicants: Mitsuru Okazaki; Youichi Kajiwara; Naoki Takahashi; Akira Shimizu - Inventors: Mitsuru Okazaki; Youichi Kajiwara; Naoki Takahashi; Akira Shimizu - Web page: https://patentgrep.com/patent/US8786092B2 ## CPC - H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies - H10W 20/43: Layouts of interconnections - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 72/00: Interconnections or connectors in packages - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer. ## Claims ### Claim 1 A semiconductor integrated circuit device, comprising: a rectangular shaped semiconductor substrate including an active region in which one or more circuits are formed; a metal wiring layer formed on or over the semiconductor substrate, wherein the semiconductor substrate is a silicon substrate; and a passivation layer covering the metal wiring layer, four corner non-wiring regions provided, respectively, at each of four corners of the semiconductor integrated circuit device, where no portion of the metal wiring layer is formed on the four corner non-wiring regions; wherein the passivation layer has a step in its upper surface at a seam between a portion thereof under which the metal wiring layer is present and a portion thereof under which the metal wiring layer is absent, and each of the corner non-wiring regions is a triangular region enclosed by a first line connecting the corner of the semiconductor integrated circuit device and a first point located on an edge extending from the corner, a second line connecting the corner and a second point located on another edge extending from the corner, and a third line connecting the first point and the second point, with no portion of the metal wiring layer inside the triangular region. ### Claim 2 (depends on 1) The semiconductor integrated circuit device of claim 1, further comprising: a barrier metal layer immediately under the metal wiring layer. ### Claim 3 (depends on 2) The semiconductor integrated circuit device of claim 2, wherein a digital circuit which does not tend to change in circuit characteristic under stress is arranged near the corner of the semiconductor substrate, and an analog circuit which tends to change in circuit characteristic under stress is arranged at a center of the semiconductor substrate. ### Claim 4 (depends on 3) The semiconductor integrated circuit device of claim 3, wherein the digital circuit includes a logic circuit such as an AND gate. ### Claim 5 (depends on 4) The semiconductor integrated circuit device of claim 4, wherein the analog circuit includes a current mirror circuit. ### Claim 6 (depends on 5) The semiconductor integrated circuit device of claim 5, wherein one side of the semiconductor substrate is at least five times as long as another side that is perpendicular to the one side. ### Claim 7 (depends on 6) The semiconductor integrated circuit device of claim 6, wherein the semiconductor integrated circuit device is a display driver or a sensor device. ### Claim 8 (depends on 1) The semiconductor integrated circuit device of claim 1 , wherein the first line and the second line each have a length of 250 μm. ### Claim 9 (depends on 8) The semiconductor integrated circuit device of claim 8, wherein a portion of the metal wiring layer is arranged straight along the third line. ### Claim 10 (depends on 8) The semiconductor integrated circuit device of claim 8, wherein a portion of the metal wiring layer is arranged in a staircase pattern along the third line. ### Claim 11 (depends on 8) The semiconductor integrated circuit device of claim 8, wherein a portion of the metal wiring layer is arranged in a wave pattern along the third line. ### Claim 12 (depends on 8) The semiconductor integrated circuit device of claim 8, wherein a portion of the metal wiring layer is arrange to be curved along a circular arc in a corner of the semiconductor substrate. ### Claim 13 (depends on 5) The semiconductor integrated circuit device of claim 5, wherein the analog circuit further includes a constant current circuit. ### Claim 14 (depends on 13) The semiconductor integrated circuit device of claim 13, wherein the analog circuit further includes a constant voltage circuit. ### Claim 15 (depends on 14) The semiconductor integrated circuit device of claim 14, wherein the analog circuit further includes a digital/analog converter circuit. ### Claim 16 (depends on 15) The semiconductor integrated circuit device of claim 15, wherein the analog circuit further includes an analog/digital converter circuit. ### Claim 17 (depends on 1) The semiconductor integrated circuit device of claim 1, further comprising an insulating layer formed under the passivation layer.