# US 8,786,088 B2 · Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,088 B2 - Document ID: US8786088B2 - Status: Granted - Kind: B2 - Application number: 12/966,302 - Filed: 2010-12-13 - Published: 2012-01-05 - Granted: 2014-07-22 - Earliest claimed: 2010-06-30 - Assignees: Globalfoundries Inc. - Applicants: Torsten Huisinga; Jens Heinrich; Kai Frohberg; Frank Feustel - Inventors: Torsten Huisinga; Jens Heinrich; Kai Frohberg; Frank Feustel - Web page: https://patentgrep.com/patent/US8786088B2 ## CPC - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10W 20/071: {of dielectric parts thereof} - H10W 20/084: {for dual-damascene structures} - H10W 20/085: {involving intermediate temporary filling with material} - H10W 20/42: Vias, e.g. via plugs - H10W 20/48: Insulating materials thereof - H10W 20/0886: {involving forming a via in a via-level dielectric prior to deposition of a trench-level dielectric} - H10W 20/0888: {wherein via-level dielectrics are compositionally different than trench-level dielectrics} - H10W 20/425: {Barrier, adhesion or liner layers} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract In complex semiconductor devices, sophisticated ULK materials may be used in metal line layers in combination with a via layer of enhanced mechanical stability by increasing the amount of dielectric material of superior mechanical strength. Due to the superior mechanical stability of the via layers, reflow processes for directly connecting the semiconductor die and a package substrate may be performed on the basis of a lead-free material system without unduly increasing yield losses. ## Claims ### Claim 1 A semiconductor device, comprising: a metallization system comprising a metal line layer formed above a substrate, said metal line layer comprising a metal line laterally embedded in a porous dielectric material, said metallization system further comprising a via layer comprising a via connecting to said metal line, said via being laterally embedded in a non-porous dielectric material along a height of said via, wherein said non-porous dielectric material comprises an etch stop layer and at least one further material formed at least locally at said via above said etch stop layer and wherein said at least one further material forms material portions, each of which is laterally embedded in a further porous dielectric material; and a bump structure configured to be connected to a complementary contact structure of a package substrate by using a lead-free solder material. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein said porous dielectric material has a dielectric constant of 2.7 or less. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein said metallization system comprises a plurality of via layers comprising vias that are laterally embedded in a non-porous dielectric material, wherein each of said via layers is formed between metal line layers comprising a porous dielectric material. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein said at least one further material forms a continuous layer outside of said via and any other via of said via layer. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein said further porous dielectric material and said porous dielectric material of said metal line layer form a continuous material. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein said bump structure comprises metal pillars. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein said bump structure comprises solder bumps comprised of a lead-free solder material. ### Claim 8 (depends on 1) The semiconductor device of claim 1, further comprising circuit elements having a critical dimension of approximately 50 nm or less. ### Claim 9 A semiconductor device, comprising: a plurality of stacked metal line layers formed above a substrate, each metal line layer comprising a plurality of metal lines formed in an ultra low-k dielectric material; at least one intermediate via layer located between two of said plurality of stacked metal line layers, said at least one intermediate via layer comprising a metal-containing via formed in a dielectric material, at least a portion of which has a greater dielectric constant than said ultra low-k dielectric material, said at least a portion extending along a total height of said via, wherein said dielectric material of greater dielectric constant forms a plurality of material portions, each of which is laterally enclosed by an ultra low-k dielectric material; and a bump structure comprising contact elements for forming an intermetallic connection with complementary contact elements of a package substrate on the basis of a lead-free contact regime wherein said plurality of material are positioned on an etch stop layer. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein said dielectric material of greater dielectric constant forms a continuous material layer outside said metal-containing via and any other via of said at least one via layer. ### Claim 11 (depends on 9) The semiconductor device of claim 9, wherein a dielectric constant of said ultra low-k dielectric material is 2.7 or less. ### Claim 12 (depends on 9) The semiconductor device of claim 9, wherein said at least one intermediate via layer comprises a nitrogen-containing etch stop layer.