# US 8,786,082 B2 · Semiconductor structure having no adjacent bumps between two adjacent pads

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- Number: US 8,786,082 B2
- Document ID: US8786082B2
- Status: Granted
- Kind: B2
- Application number: 13/671,202
- Filed: 2012-11-07
- Published: 2013-06-13
- Granted: 2014-07-22
- Earliest claimed: 2011-12-09
- Assignees: ChipMOS Technologies Inc.
- Applicants: Chipmos Technologies Inc.
- Inventors: Geng-Shin Shen
- Web page: https://patentgrep.com/patent/US8786082B2

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/652: Cross-sectional shapes
- H10W 72/90: Bond pads, in general
- H10W 74/147: {the encapsulations being multilayered}
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, at least two pads, a passivation layer, at least two under bump metallization (UBM) layers and at least two bumps. The pads are disposed adjacent to each other on the substrate along the first direction. The passivation layer covers the substrate and the peripheral upper surface of each pad to define an opening. Each of the openings defines an opening projection along the second direction. The opening projections are disposed adjacent to each other but not overlapping with each other. Furthermore, the first direction is perpendicular to the second direction. The UBM layers are disposed on the corresponding openings, and the bumps are respectively disposed on the corresponding UBM layers. With the above arrangements, the width of each bump of the semiconductor structure of the present invention could be widened without being limited by the bump pitch.

## Claims

### Claim 1

A semiconductor structure, having a first direction and a second direction, the second direction being perpendicular to the first direction, and the semiconductor structure comprising:
a substrate;
at least two pads, being disposed on the substrate adjacent to each other along the first direction;
a passivation layer, being disposed on and covering the substrate and a peripheral upper surface of each of the pads and defining an opening corresponding to each of the pads;
at least two UBM layers, being respectively disposed on the opening of each of the pads; and
at least two bumps, being respectively disposed on the at least two UBM layers,
wherein, each of the openings defines an opening projection along the second direction at a projection plane, and the two opening projections defined by any two of the adjacent openings are not overlapped with each other.

### Claim 2 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the passivation layer further comprises a protection layer that covers the substrate and the peripheral upper surface of each of the pads to define a pad opening on each of the pads, wherein each of the pad openings defines an pad opening projection along the second direction and the pad opening projections overlap with each other.

### Claim 3 (depends on 2)

The semiconductor structure as claimed in claim 2, wherein the passivation layer further comprises an insulation layer that covers the protection layer and partially covers each of the pad openings to define the opening corresponding to each of the pads.

### Claim 4 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the at least two bumps are made of Au, Ag, Cu, Ni or an alloy thereof.

### Claim 5 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the at least two bumps define at least two bump projections along the second direction, and any two of the at least two bump projections partially overlap with each other.

### Claim 6 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the at least two UBM layers are made of Ti, Cu, Vanadium, TiW or an alloy thereof.

### Claim 7 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the at least two bumps are made of an electrically conductive polymer.

### Claim 8 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the substrate is a chip.

### Claim 9 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the substrate is a wafer.

### Claim 10 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the substrate is a printed circuit board (PCB).

### Claim 11 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the substrate is a film.

### Claim 12 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the passivation layer is made of SiO2 or SiN.

### Claim 13 (depends on 1)

The semiconductor structure as claimed in claim 1, the at least two pads are in a bar shape and disposed along the second direction.

### Claim 14 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the at least two bumps are electroplated on each of the at least two UBM layers respectively.

### Claim 15 (depends on 1)

The semiconductor structure as claimed in claim 1, wherein the at least two bumps define a bump pitch which is narrower than a width of any one of the at least two bumps.

### Claim 16 (depends on 2)

The semiconductor structure as claimed in claim 2, wherein the at least two bumps define a bump pitch which is narrower than a width of any one of the at least two bumps.

### Claim 17 (depends on 3)

The semiconductor structure as claimed in claim 3, wherein the at least two bumps define a bump pitch which is narrower than a width of any one of the at least two bumps.