# US 8,786,070 B2 · Microelectronic package with stacked microelectronic elements and method for manufacture thereof

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- Number: US 8,786,070 B2
- Document ID: US8786070B2
- Status: Granted
- Kind: B2
- Application number: 13/940,582
- Filed: 2013-07-12
- Published: 2013-11-14
- Granted: 2014-07-22
- Earliest claimed: 2011-08-01
- Assignees: Tessera, Inc.
- Applicants: Tessera, Inc.
- Inventors: Hiroaki Sato; Norihito Masuda; Belgacem Haba; Ilyas Mohammed
- Web page: https://patentgrep.com/patent/US8786070B2

## CPC

- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/01: Manufacture or treatment
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/6523: {for connecting to pads at different heights at the same side of the package substrate, interposer or RDL}
- H10W 70/654: Top-view layouts
- H10W 70/655: Fan-out layouts
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/20: Configurations of stacked chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A microelectronic package may include a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing a top surface of the package. The front face of the first element may be adjacent the top surface, and the first element may overlie the front face of the second element such that at least a portion of the front face of the second element having an element contact thereon extends beyond an edge of the first element. A conductive structure may electrically connect a first terminal at the top surface to an element contact at the front face of the second element, and include a continuous monolithic metal feature extending along the top surface and through at least a portion of an encapsulant, which is between the top surface and the front face of the second element, towards the element contact.

## Claims

### Claim 1

A microelectronic package, the package having a top surface and a bottom surface remote from the top surface, the package comprising:
a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing the top surface and a rear face remote from the front face, wherein the front face of the first microelectronic element is adjacent the top surface, wherein the first microelectronic element overlies the front face of the second microelectronic element such that at least a portion of the front face of the second microelectronic element having at least one element contact thereon extends beyond an edge of the first microelectronic element;
an encapsulant between the top surface and the front face of the second microelectronic element;
at least one package terminal at the top surface, the at least one package terminal usable to connect the package to a contact of a microelectronic component external to the package; and
a conductive structure electrically connecting the at least one package terminal to the at least one element contact at the front face of the second microelectronic element, the conductive structure including a wire bond extending from the at least one element contact, through the encapsulant and to the top surface.

### Claim 2 (depends on 1)

The package of claim 1, wherein the conductive structure includes a second wire bond extending from at least one second element contact at a portion of the front face of the first microelectronic element, through the encapsulant and to the top surface, in which the second wire bond is electrically connected to the at least one package terminal.

### Claim 3 (depends on 1)

The package of claim 1 further comprising:
a substrate having a first surface and a second surface, wherein the stacked unit overlies the first surface of the substrate such that at least a portion of the first surface having at least one substrate contact thereon extends beyond an edge of the stacked microelectronic unit,
wherein the encapsulant covers at least a portion of the first surface of the substrate, and
wherein the conductive structure includes a second wire bond extending from the at least one substrate contact, through the encapsulant and to the top surface, in which the second wire bond is electrically connected to the at least one package terminal.

### Claim 4 (depends on 1)

The package of claim 1,
wherein the encapsulant is between the top surface and the rear face of the second microelectronic element, and
wherein a conductive via, electrically connected to the at least one package terminal, extends from the top surface, through a portion of the encapsulant beyond an edge of the second microelectronic element, and to the bottom surface.