# US 8,786,062 B2 · Semiconductor package and process for fabricating same

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- Number: US 8,786,062 B2
- Document ID: US8786062B2
- Status: Granted
- Kind: B2
- Application number: 12/904,799
- Filed: 2010-10-14
- Published: 2011-04-14
- Granted: 2014-07-22
- Earliest claimed: 2009-10-14
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Yuan-Chang Su; Shih-Fu Huang; Chia-Cheng Chen; Chia-Hsiung Hsieh; Tzu-Hui Chen; Kuang-Hsiung Chen; Pao-Ming Hsieh
- Inventors: Yuan-Chang Su; Shih-Fu Huang; Chia-Cheng Chen; Chia-Hsiung Hsieh; Tzu-Hui Chen; Kuang-Hsiung Chen; Pao-Ming Hsieh
- Web page: https://patentgrep.com/patent/US8786062B2

## CPC

- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H05K 1/111: {Pads for surface mounting, e.g. lay-out}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/635: {Through-vias}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 72/01308: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/07311: {Treating the bonding area before connecting, e.g. by applying flux or cleaning}
- H10W 72/30: Die-attach connectors
- H10W 72/50: Bond wires
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/737: {between a chip and a laterally-adjacent lead frame, conducting package substrate or heat sink}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier.

## Claims

### Claim 1

A semiconductor package, comprising:
a package carrier including:
a dielectric layer defining a plurality of through holes extending from a top surface of the dielectric layer to a bottom surface of the dielectric layer, wherein a first of the plurality of through holes has a first lateral extent larger than a second lateral extent of a second of the plurality of through holes;
a conductive pillar disposed within the first through hole defined by the dielectric layer; and
a conductive layer extending over a portion of the dielectric layer surrounding the first through hole defined by the dielectric layer, the conductive layer further defining a pad adjacent to the dielectric layer; and
a chip attached to the package carrier, wherein an active surface of the chip is electrically connected to the pad.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein a bottom end of the conductive pillar is concave.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein a lower surface of the conductive pillar is recessed from the bottom surface of the dielectric layer.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the conductive pillar is configured to relieve mechanical stress to the package.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, further comprising a barrier layer disposed at least partially within the first through hole defined by the dielectric layer, the barrier layer being adjacent to the conductive pillar.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein a top surface of the conductive pillar is recessed below the top surface of the dielectric layer.