# US 8,786,061 B2 · Semiconductor device

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- Number: US 8,786,061 B2
- Document ID: US8786061B2
- Status: Granted
- Kind: B2
- Application number: 13/439,025
- Filed: 2012-04-04
- Published: 2012-10-11
- Granted: 2014-07-22
- Earliest claimed: 2011-04-11
- Assignees: Sony Corporation
- Applicants: Ken Sawada
- Inventors: Ken Sawada
- Web page: https://patentgrep.com/patent/US8786061B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/611: {for connecting multiple chips together}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias}
- H10W 20/2125: {Top-view shapes}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 70/635: {Through-vias}
- H10W 90/00: Package configurations
- H10W 20/423: {Shielding layers}
- H10W 20/427: {Power or ground buses}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/271: {the arrangements being between stacked chips}
- H10W 44/209: {Vertical interconnections, e.g. vias}
- H10W 44/216: {Waveguides, e.g. strip lines}
- H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first semiconductor substrate and a second semiconductor substrate laminated with an insulating layer, a first transmission line formed on the first semiconductor substrate, the first transmission line including a signal line and a ground, a second transmission line formed on the second semiconductor substrate, the second transmission line including a signal line and a ground, a first via layer for the signal lines, the first via layer for the signal lines being formed of a conductor layer formed within a via hole, a first via layer for the grounds, the first via layer for the grounds being formed of a conductor layer formed within a via hole, and a second via layer for the grounds, the second via layer for the grounds being formed of a conductor layer formed within a via hole.

## Claims

### Claim 1

A semiconductor device comprising:
a first semiconductor substrate and a second semiconductor substrate laminated with an insulating layer interposed between the first semiconductor substrate and the second semiconductor substrate;
a first transmission line formed on said first semiconductor substrate, the first transmission line including a signal line and a ground;
a second transmission line formed on said second semiconductor substrate, the second transmission line including a signal line and a ground;
a first via layer for the signal lines, the first via layer for the signal lines being formed of a conductor layer formed within a via hole, and connected to the signal line of said first transmission line and the signal line of said second transmission line;
a first via layer for the grounds, the first via layer for the grounds being formed of a conductor layer formed within a via hole, and connected to the ground of said first transmission line and the ground of said second transmission line; and
a second via layer for the grounds, the second via layer for the grounds being formed of a conductor layer formed within a via hole, connected to the ground of said first transmission line and/or the ground of said second transmission line, and including a via layer in a shape of a band, the via layer in the shape of the band being formed so as to be opposed to said first via layer for the signal lines.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein said second via layer is formed so as to be shallower than said first via layer for the grounds.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein said first transmission line and said second transmission line are each a coplanar line.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein one of said first transmission line and said second transmission line is a coplanar line, and the other is a microstrip line.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1,
wherein said first transmission line and said second transmission line are each a microstrip line.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1,
wherein for a characteristic impedance Za of said first transmission line and a characteristic impedance Zb of said second transmission line, a characteristic impedance of a via part including said via layer for the signal lines and said second via layer is √(Za×Zb).