# US 8,786,058 B2 · Semiconductor devices and methods of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,058 B2 - Document ID: US8786058B2 - Status: Granted - Kind: B2 - Application number: 13/289,576 - Filed: 2011-11-04 - Published: 2012-05-10 - Granted: 2014-07-22 - Earliest claimed: 2010-11-08 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Kyu-Hee Han; Byung-Lyul Park; Byunghee Kim; Sanghoon Ahn; Sangdon Nam; Kyoung-Hee Kim - Inventors: Kyu-Hee Han; Byung-Lyul Park; Byunghee Kim; Sanghoon Ahn; Sangdon Nam; Kyoung-Hee Kim - Web page: https://patentgrep.com/patent/US8786058B2 ## CPC - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0245: {comprising use of blind vias during the manufacture} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/2125: {Top-view shapes} - H10W 20/217: {comprising ring-shaped isolation structures outside of the via holes} - H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 20/072: {of dielectric parts comprising air gaps} - H10W 20/46: comprising air gaps - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/07236: {Soldering or alloying} - H10W 72/07254: {changes in dispositions} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/59: Bond pads specially adapted therefor - H10W 72/879: {Bump connectors and bond wires} - H10W 72/90: Bond pads, in general - H10W 72/922: {Bond pads being integral with underlying chip-level interconnections} - H10W 72/9223: {with redistribution layers [RDL]} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device is provided. The semiconductor device includes a substrate having a via hole comprised of a first region having a first width and a second region having a second width greater than the first width, wherein at least a portion of the substrate is exposed in the via hole, and an insulating region having an air gap spaced apart from and surrounding the first region of the via hole. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor substrate having a via hole, the via hole comprising a first region having a first width and a second region having a second width greater than the first width; and an insulating region including an air gap surrounding and spaced apart from the first region of the via hole. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein a portion of the semiconductor substrate is interposed between the air gap and the first region of the via hole. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the air gap is disposed under the second region of the via hole. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein a depth of the air gap in the semiconductor substrate is less than a depth of the first region of the via hole in the semiconductor substrate. ### Claim 5 (depends on 1) The semiconductor device of claim 1, comprising a plurality of air gaps surrounding and spaced apart from the first region of the via hole, wherein a portion of the semiconductor substrate is interposed between adjacent air gaps of the plurality of air gaps. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein a lower portion of the second region is connected to the first region of the via hole and has a narrowing width. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the insulating region further comprises an insulating film provided along a side of the via hole. ### Claim 8 (depends on 7) The semiconductor device of claim 7, wherein the insulating film fills a portion of the air gap. ### Claim 9 (depends on 7) The semiconductor device of claim 7, further comprising a conductive film filling the via hole, wherein a contact area of the conductive film in the second region of the via hole is greater than a contact area of the conductive film in the first region of the via hole. ### Claim 10 A semiconductor device comprising: a semiconductor substrate; a through silicon via extending from a first surface of the semiconductor substrate to a second surface of the semiconductor substrate opposite the first surface, wherein the through silicon via includes a first region having a first width and a second region having a second width greater than the first width; and an air gap surrounding and spaced apart from the first region of the through silicon via, wherein the air gap is positioned under the second region of the through silicon via. ### Claim 11 (depends on 10) The semiconductor device of claim 10, further comprising an insulating film positioned between the through silicon via and the semiconductor substrate. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein a portion of the insulating film extends into the air gap. ### Claim 13 (depends on 11) The semiconductor device of claim 11, wherein the insulating film extends onto the first surface of the semiconductor substrate. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein an opening in the insulating film exposes a contact pad positioned on the first surface of the semiconductor substrate.