# US 8,786,057 B2 · Integrated circuit on corrugated substrate

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- Number: US 8,786,057 B2
- Document ID: US8786057B2
- Status: Granted
- Kind: B2
- Application number: 12/178,495
- Filed: 2008-07-23
- Published: 2008-11-27
- Granted: 2014-07-22
- Earliest claimed: 2005-07-01
- Assignees: Synopsys, Inc.
- Applicants: Tsu-Jae King; Victor Moroz
- Inventors: Tsu-Jae King; Victor Moroz
- Web page: https://patentgrep.com/patent/US8786057B2

## CPC

- H10D 62/57: the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/834: {comprising FinFETs}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/798: {being provided in or under the channel regions}
- H10W 46/503: {Located in scribe lines}
- Y10S 438/974: Substrate surface preparation
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

## Claims

### Claim 1

A semiconductor substrate comprising:
a plurality of parallel semiconductor ridges formed on a bulk substrate;
a ridge insulator material between each of the plurality of parallel semiconductor ridges, wherein the ridge insulator material is formed between sub-surface heavily doped regions of the plurality of parallel semiconductor ridges; and
a plurality of die locations,
wherein a first depth of sub-surface heavily doped regions of a first plurality of parallel semiconductor ridges is different than a second depth of sub-surface heavily doped regions of a second plurality of parallel semiconductor ridges.