# US 8,786,056 B2 · Semiconductor light emitting elements comprising a plating substrate with a projecting tab, or comprising an exposed seed layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,056 B2 - Document ID: US8786056B2 - Status: Granted - Kind: B2 - Application number: 13/156,150 - Filed: 2011-06-08 - Published: 2011-12-15 - Granted: 2014-07-22 - Earliest claimed: 2010-06-09 - Assignees: Nichia Corporation - Applicants: Kentaro Watanabe; Giichi Marutsuki; Yuya Yamakami - Inventors: Kentaro Watanabe; Giichi Marutsuki; Yuya Yamakami - Web page: https://patentgrep.com/patent/US8786056B2 ## CPC - H10H 20/0137: {the light-emitting regions comprising nitride materials} - H10H 20/01335: {the light-emitting regions comprising nitride materials} - H10H 20/018: {Bonding of wafers} - H10H 20/811: having quantum effect structures or superlattices, e.g. tunnel junctions - H10H 20/824: comprising only Group III-V materials, e.g. GaP - H10H 20/036: {of packages} - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS ## Abstract A method of forming a semiconductor light emitting element. The method can include forming a seed layer on a semiconductor layer assembly including at least one nitride semiconductor layer. An insulating mask can be formed on the seed layer. The insulating mask can include a plurality of element areas separated by cross spaces. Each element area of the plurality of element areas can be connected to at least one of the other element areas of the plurality of element areas. The seed layer can be plated such that a plating substrate is formed in each of the plurality of element areas. ## Claims ### Claim 1 An apparatus comprising: a first electrode layer disposed on at least one nitride semiconductor layer; a seed layer disposed on the first electrode layer; and a plating layer disposed on the seed layer opposite to the at least one nitride semiconductor layer, wherein the nitride semiconductor layer includes a plurality of grooves formed in a longitudinal direction and a plurality of grooves formed in a lateral direction, wherein the plating layer includes a plurality of plating substrates and a plurality of cross-shaped spaces, wherein the plating substrates are partially separated from one another by legs of the cross-shaped spaces, wherein the plating substrates are partially connected to one another via a part of the plating layer disposed between legs of the cross-shaped spaces, and wherein each plating substrate is substantially rectangular with a tab projecting from at least one side of the plating substrate wherein an entirety of a surface of the plating layer that faces the nitride semiconductor layer, including a surface of the part of the plating layer disposed between the legs of the cross-shaped spaces, is in a single plane. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the seed layer has a thickness greater than or equal to 0.1 micrometers and less than or equal to 0.5 micrometers. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the plating substrate has a thickness greater than or equal to 80 micrometers and less than or equal to 120 micrometers. ### Claim 4 (depends on 1) The apparatus of claim 1, further comprising a second electrode layer disposed on the at least one nitride semiconductor layer, wherein the second electrode layer is located opposite of the first electrode layer. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the plurality of grooves are aligned with the cross-shaped spaces. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein: the seed layer comprises at least one of Ni, Cu, or Au; the plating substrate comprises at least one of Ni, Cu, or Au; and the at least one nitride semiconductor layer comprises a p-type nitride semiconductor layer, a n-type nitride semiconductor layer, and an active layer. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein each of the cross-shaped spaces comprises four rectangular legs, and wherein a length of each of the four rectangular legs is less than half of a side length of a corresponding plating substrate of the plurality of plating substrates. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein a width of each of the four rectangular legs of the each of the cross-shaped spaces is greater than or equal to 40 micrometers. ### Claim 9 (depends on 7) The apparatus of claim 7, wherein a width of at least one of the grooves of the nitride semiconductor layer is wider than a width of a leg of a corresponding cross-shaped space of the plating substrate. ### Claim 10 (depends on 9) The apparatus of claim 9, further comprising: a passivation layer disposed on the nitride semiconductor layer, wherein a width of the passivation layer is wider than a width of a corresponding groove of the nitride semiconductor layer. ### Claim 11 An apparatus comprising: a first electrode layer on at least one nitride semiconductor layer, wherein the first electrode layer includes a first electrode; a seed layer on the first electrode layer opposite to the nitride semiconductor layer; a plating substrate on the seed layer; and a second electrode layer disposed on the at least one nitride semiconductor layer, wherein the second electrode layer is located opposite of the first electrode, wherein the plating substrate includes at least one tab projecting from at least one side of the plating substrate in a plan view of the apparatus wherein an entirety of a surface of the latin substrate that faces the nitride semiconductor layer, including a surface of the at least one tab, is in a single plane. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein the at least one tab covers less than half of a corresponding side of the plating substrate in a plan view of the apparatus. ### Claim 13 (depends on 11) The apparatus of claim 11, wherein at least one tab projects less than 20 micrometers from the at least one side of the plating substrate. ### Claim 14 (depends on 11) The apparatus of claim 11, wherein the seed layer has a thickness greater than or equal to 0.1 micrometers and less than or equal to 0.5 micrometers. ### Claim 15 (depends on 11) The apparatus of claim 11, wherein the plating substrate has a thickness greater than or equal to 80 micrometers and less than or equal to 120 micrometers. ### Claim 16 (depends on 11) The apparatus of claim 11, wherein: the seed layer comprises at least one of Ni, Cu, or Au; the plating substrate comprises at least one of Ni, Cu, or Au; and the at least one nitride semiconductor layer comprises a p-type nitride semiconductor layer, a n-type nitride semiconductor layer, and an active layer. ### Claim 17 (depends on 11) The apparatus of claim 11, wherein the plating substrate is substantially rectangular. ### Claim 18 (depends on 11) The apparatus of claim 11, wherein the semiconductor layer is substantially rectangular. ### Claim 19 (depends on 11) The apparatus of claim 11, wherein the plating substrate was formed from a plating layer including a plurality of plating substrates separated by cross-shaped spaces, and wherein each plating substrate of the plurality of plating substrates was connected to at least one of the other plating substrates of the plurality of plating substrates. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein each of the cross-shaped spaces comprises four rectangular legs, and wherein a length of each of the four rectangular legs is less than half of a side length of a corresponding plating substrate of the plurality of plating substrates. ### Claim 21 (depends on 20) The apparatus of claim 20, wherein a width of each of the four rectangular legs of the cross-shaped spaces is greater than or equal to 40 micrometers. ### Claim 22 (depends on 20) The apparatus of claim 20, wherein the nitride semiconductor layer was formed from a pre-dicing nitride semiconductor layer that includes a plurality of grooves formed in a longitudinal direction and a lateral direction, and wherein a width of at least one of the grooves of the pre-dicing nitride semiconductor layer is wider than a width of a leg of a corresponding cross-shaped space of the plating substrate. ### Claim 23 (depends on 20) The apparatus of claim 20, further comprising: a passivation layer disposed on the nitride semiconductor layer, wherein the nitride semiconductor layer was formed from a pre-dicing nitride semiconductor layer that includes a plurality of grooves formed in a longitudinal direction and a lateral direction, and wherein a width of the passivation layer is wider than a width of a corresponding groove of the pre-dicing nitride semiconductor layer. ### Claim 24 An apparatus comprising: a first electrode layer disposed on at least one nitride semiconductor layer; a seed layer disposed on the first electrode layer; and a plating layer disposed on the seed layer opposite to the nitride semiconductor layer, wherein the nitride semiconductor layer includes a plurality of grooves formed in a longitudinal direction and a lateral direction, wherein the plating layer includes a plurality of plating substrates and a plurality of spaces, wherein the plating substrates are partially separated from one another by the spaces, wherein the plating substrates are partially connected to one another via a part of the plating layer disposed between the spaces, and wherein the seed layer is exposed at bottoms of the spaces. ### Claim 25 (depends on 24) The apparatus of claim 24, wherein the seed layer has a thickness greater than or equal to 0.1 micrometers and less than or equal to 0.5 micrometers. ### Claim 26 (depends on 24) The apparatus of claim 24, wherein the plating substrate has a thickness greater than or equal to 80 micrometers and less than or equal to 120 micrometers. ### Claim 27 (depends on 24) The apparatus of claim 24, further comprising a second electrode layer disposed on the at least one nitride semiconductor layer, wherein the second electrode layer is located opposite of the first electrode layer. ### Claim 28 (depends on 24) The apparatus of claim 24, wherein the plurality of grooves are aligned with the spaces. ### Claim 29 (depends on 24) The apparatus of claim 24, wherein: the seed layer comprises at least one of Ni, Cu, or Au; the plating substrate comprises at least one of Ni, Cu, or Au; and the at least one nitride semiconductor layer comprises a p-type nitride semiconductor layer, a n-type nitride semiconductor layer, and an active layer. ### Claim 30 (depends on 24) The apparatus of claim 24, wherein each plating substrate is substantially rectangular with a tab projecting from at least one side of the plating substrate. ### Claim 31 (depends on 24) The apparatus of claim 24, wherein a width of at least one of the grooves of the nitride semiconductor layer is wider than a width of a leg of a corresponding space of the plating substrate. ### Claim 32 (depends on 24) The apparatus of claim 24, further comprising: a passivation layer disposed on the nitride semiconductor layer, wherein a width of the passivation layer is wider than a width of a corresponding groove of the nitride semiconductor layer.