# US 8,786,055 B2 · Solid-state imaging device, method for manufacturing solid-state imaging device, method for manufacturing solid-state imaging element, and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,055 B2 - Document ID: US8786055B2 - Status: Granted - Kind: B2 - Application number: 12/948,029 - Filed: 2010-11-17 - Published: 2011-06-02 - Granted: 2014-07-22 - Earliest claimed: 2009-11-30 - Assignees: Sony Corporation - Applicants: Hiroyuki Kawashima - Inventors: Hiroyuki Kawashima - Web page: https://patentgrep.com/patent/US8786055B2 ## CPC - H10F 39/811: {Interconnections} - H10F 39/011: {Manufacture or treatment of image sensors covered by group H10F39/12} - H10F 39/182: {Colour image sensors} - H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes} - H10F 39/8053: {Colour filters} - H10F 39/8063: {Microlenses} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract A solid-state imaging device includes a semiconductor substrate configured to include a solid-state imaging element that is provided with a photoelectric conversion region, and a scribe line region that is provided along a periphery of the solid-state imaging element, a wiring layer that is formed to be layered on the semiconductor substrate, a support substrate that is formed to be layered on the wiring layer, and a groove that is provided between a blade region in the scribe line region and the solid-state imaging element, in the semiconductor substrate and penetrates through the semiconductor substrate. ## Claims ### Claim 1 A solid-state imaging device, comprising: a semiconductor substrate configured to include a solid-state imaging element that is provided with a photoelectric conversion region, and a scribe line region that is provided along a periphery of the solid-state imaging element; a wiring layer that is formed to be layered on the semiconductor substrate, wherein the wiring layer includes a guard ring layer in a region corresponding to a region, the region being positioned between a blade region in the scribe line region and the solid-state imaging element, of the semiconductor substrate, and wherein the wiring layer and the guard ring layer include the same material; a support substrate that is formed to be layered on the wiring layer; and a groove that is provided in the semiconductor substrate between the blade region in the scribe line region and the solid-state imaging element, wherein the groove penetrates through the semiconductor substrate, wherein a depth of the groove is equal to a depth of the semiconductor substrate, wherein the groove contains a chipping prevention wall, and wherein the chipping prevention wall does not extend into the wiring layer. ### Claim 2 (depends on 1) The solid-state imaging device according to claim 1, wherein the guard ring layer is provided in a region corresponding to a region, the region being positioned between the blade region and the groove, of the semiconductor substrate. ### Claim 3 (depends on 1) The solid-state imaging device according to claim 1, wherein at least a part of the groove is filled with a predetermined material to form the chipping prevention wall. ### Claim 4 (depends on 1) The solid-state imaging device according to claim 1, wherein the whole of the groove is filled with a predetermined material to form the chipping prevention wall. ### Claim 5 (depends on 1) The solid-state imaging device of claim 1, wherein the chipping prevention wall includes SiN that fills the groove. ### Claim 6 (depends on 1) The solid-state imaging device of claim 1, wherein at least a portion of the inside of the groove is not filled with any material. ### Claim 7 (depends on 1) The solid-state imaging device of claim 1, wherein the chipping prevention wall includes at least one of a Ti layer, a TiN layer, a Ta layer and a TaN layer on a wall surface of the groove, and at least one of AL or ALCu filling an inside of the groove. ### Claim 8 (depends on 1) The solid-state imaging device of claim 1, wherein the chipping prevention wall includes at least one of a Ti layer, a TiN layer, a Ta layer, and a TaN layer is formed on a wall surface of the groove, and Cu fills an inside of the groove. ### Claim 9 (depends on 1) The solid-state imaging device of claim 1, wherein the chipping prevention wall includes at least one of a Ti layer or a TiN layer formed on a wall surface of the groove, and tungsten fills an inside of the groove. ### Claim 10 (depends on 1) The solid-state imaging device of claim 1, wherein the chipping prevention wall includes SiO2 that fills the groove. ### Claim 11 (depends on 1) The solid-state imaging device of claim 1, wherein the chipping prevention wall includes SiOC that fills the groove. ### Claim 12 A semiconductor device, comprising: a first semiconductor substrate configured to include a semiconductor chip and a scribe line region that is provided along a periphery of the semiconductor chip; a wiring layer that is formed to be layered on the first semiconductor substrate, wherein the wiring layer includes a guard ring layer in a region corresponding to a region, the region being positioned between a blade region in the scribe line region and the semiconductor chip, of the semiconductor substrate, and wherein the wiring layer and the guard ring layer include the same material; a second semiconductor substrate that is formed to be layered on the wiring layer; and a groove that is provided in the first semiconductor substrate between the blade region in the scribe line region and the semiconductor chip, wherein the groove penetrates through the first semiconductor substrate, wherein a depth of the groove is equal to the depth of the semiconductor substrate, wherein the groove contains a chipping prevention wall, and wherein the chipping prevention wall does not extend into the wiring layer. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the chipping prevention wall includes at least one of: a SiN layer and a SiO2 layer on a wall surface of the groove; SiN that fills the groove; at least one of a Ti layer, a TiN layer, a Ta layer and a TaN layer on a wall surface of the groove, and at least one of AL or ALCu filling an inside of the groove; at least one of a Ti layer, a TiN layer, a Ta layer, and a TaN layer is formed on a wall surface of the groove, and Cu fills an inside of the groove; at least one of a Ti layer or a TiN layer formed on a wall surface of the groove, and tungsten fills an inside of the groove; SiO2 that fills the groove; and SiOC that fills the groove. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein at least a portion of the inside of the groove is not filled with any material. ### Claim 15 A solid-state imaging device, comprising: a semiconductor substrate configured to include a solid-state imaging element that is provided with a photoelectric conversion region, and a scribe line region that is provided along a periphery of the solid-state imaging element; a wiring layer that is formed to be layered on the semiconductor substrate, wherein the wiring layer includes a guard ring layer in a region corresponding to a region, the region being positioned between a blade region in the scribe line region and the solid-state imaging element, of the semiconductor substrate, and wherein the wiring layer and the guard ring layer include the same material; a support substrate that is formed to be layered on the wiring layer; and a groove that is provided in the semiconductor substrate between the blade region in the scribe line region and the solid-state imaging element, wherein the groove penetrates through the semiconductor substrate; a chipping prevention wall formed in the groove, wherein the chipping prevention wall includes polysilicon filling an inside of the groove, wherein the chipping prevention wall does not extend into the wiring layer, and wherein at least one of a SiN layer and a SiO2 layer is formed on a wall surface of the groove.