# US 8,786,054 B2 · Structure for integrated circuit alignment

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- Number: US 8,786,054 B2
- Document ID: US8786054B2
- Status: Granted
- Kind: B2
- Application number: 12/619,460
- Filed: 2009-11-16
- Published: 2011-05-19
- Granted: 2014-07-22
- Earliest claimed: 2009-11-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Yu-Chyi Harn; Sophia Wang; Chun-Hung Lin; Hsien-Wei Chen; Ming-Yen Chiu
- Inventors: Yu-Chyi Harn; Sophia Wang; Chun-Hung Lin; Hsien-Wei Chen; Ming-Yen Chiu
- Web page: https://patentgrep.com/patent/US8786054B2

## CPC

- G03F 9/7084: {Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels}
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)

## Abstract

A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.

## Claims

### Claim 1

A semiconductor wafer comprising:
an exposure field;
a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and
a die alignment mark disposed between the seal ring region and the corner stress relief region without being disposed within any corner stress relief region and any seal ring region,
wherein the die alignment mark is further disposed such that there is no seal ring region between the die alignment mark and the integrated circuit region, and
wherein the corner stress relief region is free of any seal ring region.

### Claim 2 (depends on 1)

The wafer of claim 1 further comprising:
a scribe line defining the perimeter of the exposure field; and
an exposure field alignment mark disposed within the scribe line defining the perimeter of the exposure field.

### Claim 3 (depends on 1)

The wafer of claim 1 wherein the alignment mark comprises a box-in-box alignment pattern.

### Claim 4 (depends on 1)

The wafer of claim 1 wherein the alignment mark includes at least one overlay mark.

### Claim 5 (depends on 4)

The wafer of claim 4 wherein the overlay mark is formed in an active (OD) layer, a poly (POLY) layer, and/or a contact (CO) layer.

### Claim 6 (depends on 1)

The wafer of claim 1 wherein the die alignment mark comprises a first alignment mark and a second alignment mark.

### Claim 7

A semiconductor wafer comprising:
an exposure field;
a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and
a die alignment mark disposed between the seal ring region and the corner stress relief region without being disposed within any corner stress relief region and any seal ring region,
wherein the corner stress relief region is free of any seal ring region,
wherein there is not any seal ring region between the die alignment mark and the integrated circuit region, and
wherein the die alignment mark comprises a first alignment mark and a second alignment mark.

### Claim 8 (depends on 7)

The wafer of claim 7 further comprising a plurality of layers including an active (OD) layer, a poly (POLY) layer, and/or a contact (CO) layer.

### Claim 9 (depends on 8)

The wafer of claim 8 wherein the first alignment mark includes an overlay mark formed in at least one of the OD, POLY, or CO layers.

### Claim 10

A method comprising:
providing a semiconductor wafer;
defining a field on the semiconductor wafer, wherein a perimeter of the field is defined by a scribe line;
defining a die area within the field, wherein a perimeter of the die is defined by a scribe line;
forming an alignment mark within the scribe line defining the perimeter of the field; and
forming an alignment mark in a corner portion of the die area such that the alignment mark in the corner portion is disposed between a seal ring and a corner stress relief portion and between the seal ring and a circuit region without being disposed within any corner stress relief portion and any seal ring,
wherein there is not any seal ring between the alignment mark in the corner portion and the circuit region,
wherein the corner stress relief portion is free of any seal ring.

### Claim 11 (depends on 10)

The method of claim 10 wherein forming the alignment marks comprises utilizing a box-in-box alignment pattern.

### Claim 12 (depends on 10)

The method of claim 10 wherein forming the alignment mark in the corner portion of the die area comprises:
forming the seal ring in the die area; and
forming the corner stress relief portion in the die area.

### Claim 13 (depends on 10)

The method of claim 10 wherein forming the alignment mark in the corner portion of the die area includes forming an overlay mark in an active (OD) layer, a poly (POLY) layer, and/or a contact (CO) layer.

### Claim 14 (depends on 10)

The method of claim 10 further comprising:
performing a pattern recognition technique to align a mask with the alignment marks; and
exposing the semiconductor wafer to form an integrated circuit region.

### Claim 15 (depends on 10)

The method of claim 10, wherein forming the alignment mark in the corner portion of the die area includes forming a first alignment mark and a second alignment mark, wherein the first and second alignment marks include a combination of overlay marks, the first alignment mark combination being different than the second alignment mark combination.

### Claim 16 (depends on 1)

The wafer of claim 1, wherein the die alignment mark includes a first alignment mark and a second alignment mark, wherein the first and second alignment marks include a combination of overlay marks, the first alignment mark combination being different than the second alignment mark combination.

### Claim 17 (depends on 7)

The wafer of claim 7, further comprising:
a scribe line defining the perimeter of the exposure field; and
an exposure field alignment mark disposed within the scribe line defining the perimeter of the exposure field.

### Claim 18 (depends on 9)

The wafer of claim 9, wherein the second alignment mark combination is without an overlay mark formed in at least one of the OD, POLY, or CO layers.

### Claim 19 (depends on 7)

The wafer of claim 7, wherein the first and second alignment marks include a combination of overlay marks, the first alignment mark combination being different than the second alignment mark combination.

### Claim 20 (depends on 1)

The wafer of claim 1, wherein there is no other seal ring region closer to the die than the seal ring region.