# US 8,786,047 B2 · Semiconductor device with isolation layer, electronic device having the same, and method for fabricating the same

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- Number: US 8,786,047 B2
- Document ID: US8786047B2
- Status: Granted
- Kind: B2
- Application number: 13/544,411
- Filed: 2012-07-09
- Published: 2013-09-26
- Granted: 2014-07-22
- Earliest claimed: 2012-03-26
- Assignees: SK hynix Inc.
- Applicants: Hyung-Hwan Kim; Bong-Ho Choi; Jin-Yul Lee; Seung-Seok Pyo
- Inventors: Hyung-Hwan Kim; Bong-Ho Choi; Jin-Yul Lee; Seung-Seok Pyo
- Web page: https://patentgrep.com/patent/US8786047B2

## CPC

- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.

## Claims

### Claim 1

A semiconductor device with an isolation layer buried in a trench, comprising:
an interface layer formed on the surface of the trench;
a buffer layer formed in the interface layer at a bottom corner of the trench;
a liner layer formed over the interface layer; and
a gap-fill layer gap-filling the trench over the liner layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the interface layer comprises a stacked layer of first and second intermediate interface layers, and
the buffer layer is formed between the first and second intermediate interface layers.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first intermediate interface layer comprises oxide formed by thermal oxidation, the second intermediate interface layer comprises oxide formed by chemical vapor deposition (CVD), and the buffer layer comprises nitride.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the trench comprises a micro-trench formed at the bottom corner thereof, and
the buffer layer fills the micro-trenches.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the interface layer comprises oxide, the liner layer and the buffer layer comprise nitride, and the gap-fill layer comprises a spin-on dielectric.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the liner layer is formed on sidewalls of the trench to fill a lower part of the trench, and
the gap-fill layer gap-fills the rest of the trench over the liner layer.

### Claim 7

A semiconductor device, comprising:
a first interface layer formed over the surface of a first trench;
a first gap-fill layer gap-filling the first trench over the first interface layer;
a second interface layer formed over the surface of a second trench of a substrate;
a buffer layer formed in the second interface layer at a bottom corner of the second trench;
a liner layer formed over the second interface layer; and
a second gap-fill layer gap-filling the second trench over the liner layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the substrate comprises a cell region and a peripheral circuit region,
wherein the first trench is formed in the cell region, and the second trench is formed in the peripheral circuit region, and the second trench has a critical dimension (CD) greater than the first trench.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the second interface layer comprises a stacked layer of first and second intermediate interface layers, and
the buffer layer is inserted between the first and second intermediate interface layers.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, wherein the first interface layer comprises oxide formed by thermal oxidation, the second interface layer comprises oxide formed by chemical vapor deposition (CVD), and the buffer layer comprises nitride.

### Claim 11 (depends on 7)

The semiconductor device of claim 7, wherein the first and second interface layers comprise oxide, the first gap-fill layer, the liner layer, and the buffer layer comprise nitride, and the second gap-fill layer comprises a spin-on dielectric.

### Claim 12

A semiconductor device with an isolation layer buried in a trench, comprising:
a first intermediate interface layer formed on the surface of the trench;
a buffer layer formed on the first intermediate interface layer at a bottom corner of the trench;
a second intermediate interface layer formed on the first intermediate interface layer and the buffer layer;
a liner layer formed over the second intermediate interface layer; and
a gap-fill layer gap-filling the trench over the liner layer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the trench comprises a micro-trench formed at the bottom corner thereof, and
the buffer layer fills the micro-trench.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein the first and second intermediate interface layers comprise oxide, the liner layer and the buffer layer comprise nitride, and the gap-fill layer comprises a spin-on dielectric.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the first intermediate interface layer comprises oxide formed by thermal oxidation, and the second intermediate interface layer comprises oxide formed by CVD.

### Claim 16

An electronic device, comprising:
an isolation layer comprising a trench formed in a substrate, an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer; and
unit components isolated by the isolation layer.

### Claim 17

An electronic device, comprising: a first isolation layer comprising a first interface layer formed on the surface of a first trench and a first gap-fill layer formed on the first interface layer and gap-filling the first trench;
a second isolation layer comprising a second interface layer formed on the surface of a second trench, a buffer layer formed in the second interface layer at a bottom corner of the second trench, a liner layer formed on the second interface layer, and a second gap-fill layer gap-filling the second trench over the liner layer; and
unit components isolated by the first and second isolations,
wherein the second trench has a critical dimension (CD) greater than the first trench.