# US 8,786,046 B2 · Semiconductor device and method for manufacturing the same

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- Number: US 8,786,046 B2
- Document ID: US8786046B2
- Status: Granted
- Kind: B2
- Application number: 13/910,352
- Filed: 2013-06-05
- Published: 2013-10-10
- Granted: 2014-07-22
- Earliest claimed: 2009-11-19
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Tomohiro Tamaki; Yoshito Nakazawa; Satoshi Eguchi
- Web page: https://patentgrep.com/patent/US8786046B2

## CPC

- H10D 30/665: {having edge termination structures}
- H10D 12/035: {Etching a recess in the emitter region (having a recessed gate H10D12/038)}
- H10D 12/441: {Vertical IGBTs}
- H10D 12/461: {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/111: {Field plates}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate of a first conductive type having first and second sides arranged along a first direction, and third and fourth sides arranged along a second direction which is perpendicular to the first direction;
an epitaxial layer of the first conductive type formed on the semiconductor substrate;
a cell region arranged in the epitaxial layer;
a plurality of power MOSFETs formed in the cell region;
a first peripheral region arranged in the epitaxial layer and arranged between the cell region and the first side;
a second peripheral region arranged in the epitaxial layer and arranged between the cell region and the second side;
a third peripheral region arranged in the epitaxial layer and arranged between the cell region and the third side; and
a fourth peripheral region arranged in the epitaxial layer and arranged between the cell region and the fourth side,
wherein the first peripheral region has a plurality of first columns of the second conductive type opposite to the first conductive type which are formed in the epitaxial layer and which extend along the first direction,
wherein the second peripheral region has a plurality of second columns of the second conductive type which are formed in the epitaxial layer and which extend along the first direction,
wherein the third peripheral region has a plurality of third columns of the second conductive type which are formed in the epitaxial layer and which extend along the second direction,
wherein the fourth peripheral region has a plurality of fourth columns of the second conductive type which are formed in the epitaxial layer and which extend along the second direction,
wherein the cell region has a plurality of fifth columns of the second conductive type which are formed in the epitaxial layer and which extend along the first direction,
wherein resurf regions of the second conductive type are formed in the epitaxial layer and are arranged at upper portions of the first, second, third and fourth columns,
wherein a plurality of gate electrodes of the power MOSFETs are formed over the epitaxial layer of the cell region,
wherein a plurality of well regions of the second conductive type are formed in the epitaxial layer of the cell region, are arranged at upper portions of the fifth columns and have higher impurity concentration than the resurf regions,
wherein a plurality of source regions of the power MOSFETs of the first conductive type are formed in the well regions,
wherein, in the first direction, the cell region, the first peripheral region and the second peripheral region are arranged between the third peripheral region and the fourth peripheral region, and
wherein the third column and the fourth column extend along the second direction in order to abut the cell region, the first peripheral region and the second peripheral region in the first direction.

### Claim 2 (depends on 1)

A semiconductor device according to claim 1,
wherein a guard ring is formed over the epitaxial layer, is formed of a metal film and is arranged along each of the first, second, third and fourth sides in order to surround each of the first, second, third and fourth peripheral regions.

### Claim 3 (depends on 1)

A semiconductor device according to claim 1,
wherein the first, second, third, fourth and fifth columns are physically separated from each other.

### Claim 4 (depends on 1)

A semiconductor device according to claim 1,
wherein the resurf regions of the first, second, third and fourth peripheral regions are physically integrated.

### Claim 5 (depends on 1)

A semiconductor device according to claim 1,
wherein the first, second, third, fourth and fifth columns are formed by an epitaxial growth method and are buried in trenches which are formed in the epitaxial layer.

### Claim 6 (depends on 1)

A semiconductor device according to claim 1,
wherein the first conductive type is an n-type, and wherein the second conductive type is a p-type.

### Claim 7 (depends on 1)

A semiconductor device according to claim 1,
wherein the power MOSFETs are not formed in the first, second, third and fourth peripheral regions.