# US 8,786,045 B2 · Power semiconductor devices having termination structures > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,045 B2 - Document ID: US8786045B2 - Status: Granted - Kind: B2 - Application number: 12/878,429 - Filed: 2010-09-09 - Published: 2011-01-06 - Granted: 2014-07-22 - Earliest claimed: 2003-05-20 - Assignees: Fairchild Semiconductor Corporation - Applicants: Ashok Challa; Jaegil Lee; Jinyoung Jung; Hocheol Jang - Inventors: Ashok Challa; Jaegil Lee; Jinyoung Jung; Hocheol Jang - Web page: https://patentgrep.com/patent/US8786045B2 ## CPC - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs} - H10D 12/461: {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)} - H10D 30/635: {having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs} - H10D 30/665: {having edge termination structures} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 30/669: {having voltage-sensing or current-sensing structures, e.g. emulator sections or overcurrent sensing cells} - H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 64/111: {Field plates} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 84/143: {the built-in components being PN junction diodes} - H10D 84/144: {in antiparallel diode configurations} - H10D 84/146: {the built-in components being Schottky barrier diodes} - H10P 50/242: {of Group IV materials} - H10P 50/244: {comprising alternated and repeated etching and passivation steps} - H10P 50/283: {by chemical means} - H10P 72/74: {using temporarily an auxiliary support} - H02M 3/00: Conversion of DC power input into DC power output - H02M 3/33592: {having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer} - H02M 7/48: using discharge tubes with control electrode or semiconductor devices with control electrode - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D 64/516: {the thicknesses being non-uniform} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates} - H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10P 30/221: {characterised by the angle between the ion beam and the mask} - H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)} - H10P 72/7422: {used to protect an active side of a device or wafer} - H10P 72/7432: {used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate} - H10W 70/465: {Bumps or wires} - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract In one general aspect, a termination structure can include a plurality of pillars of a first conductivity type formed inside a termination region of a second conductivity type opposite the first conductivity type where the plurality of pillars define a plurality of concentric rings surrounding an active area of a semiconductor device. The termination structure can include a conductive field plate where the plurality of pillars includes a first pillar coupled to the conductive field plate. The termination structure can include a dielectric layer where the plurality of pillars include a second pillar insulated by the dielectric layer from a portion of the conductive field plate disposed directly above the second pillar included in the plurality of pillars. ## Claims ### Claim 1 A termination structure, comprising: a plurality of pillars of a first conductivity type formed inside a termination region of a second conductivity type opposite the first conductivity type, the plurality of pillars defining a plurality of concentric rings surrounding an active area of a semiconductor device; a conductive field plate, the plurality of pillars including a first pillar coupled to the conductive field plate; and a dielectric layer, the plurality of pillars including a second pillar insulated by the dielectric layer from a portion of the conductive field plate disposed directly above the second pillar included in the plurality of pillars. ### Claim 2 (depends on 1) The termination structure of claim 1, wherein the conductive field plate is a first conductive field plate coupled to the first pillar, the conductive field plate is made of a conductive material that covers and is dielectrically isolated from the second pillar by the dielectric layer, the termination structure further comprising: a second conductive field plate coupled to a third pillar from the plurality of pillars. ### Claim 3 (depends on 1) The termination structure of claim 1, wherein the conductive field plate is coupled to ground. ### Claim 4 (depends on 1) The termination structure of claim 1, wherein a center-to-center spacing between each pair of adjacent pillars from the plurality of pillars varies with a distance from an edge of the active area. ### Claim 5 (depends on 1) The termination structure of claim 1, wherein a center-to-center spacing between each pair of adjacent pillars from the plurality of pillars increases with a distance from an edge of the active area. ### Claim 6 (depends on 1) The termination structure of claim 1, wherein a width of each pillar from the plurality of pillars varies with a distance from an edge of the active area. ### Claim 7 (depends on 1) The termination structure of claim 1, wherein a width of each pillar from the plurality of pillars decreases with a distance from an edge of the active area. ### Claim 8 (depends on 1) The termination structure of claim 1, wherein a top surface of the second pillar from the plurality of pillars is covered by the dielectric layer. ### Claim 9 (depends on 1) The termination structure of claim 1, wherein the conductive field plate coupled to the first pillar extends over and is insulated from the second pillar from the plurality of pillars by the dielectric layer. ### Claim 10 (depends on 1) The termination structure of claim 1, wherein the first pillar has a length at least five times greater than a width of the first pillar. ### Claim 11 (depends on 1) The termination structure of claim 1, wherein the plurality of pillars are p-type pillars, the p-type pillars decrease in charge with distance from the active area such that a net n-type balance charge is formed in at least a portion of the termination region. ### Claim 12 (depends on 1) The termination structure of claim 1, wherein at least a portion of the termination region of the second conductivity type is an epitaxial layer, the first pillar extends to a depth more than half of a thickness of the epitaxial layer. ### Claim 13 An apparatus, comprising: a first conductive field plate; a second conductive field plate; a dielectric layer; and a plurality of pillars of a first conductivity type formed inside a termination region of a second conductivity type opposite the first conductivity type, the plurality of pillars defining a plurality of concentric rings disposed outside of an active area of a semiconductor device, the plurality of pillars including a first pillar coupled to the first conductive field plate and including a second pillar coupled to the second conductive field plate, the plurality of pillars including a third pillar isolated from the second conductive field plate by the dielectric layer, the dielectric layer being contiguous between the first pillar included in the plurality of pillars and the second pillar included in the plurality of pillars, the plurality of pillars being p-type pillars, the p-type pillars decreasing in charge with distance from the active area such that a net n-type balance charge is formed in at least a portion of the termination region. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein at least a portion of the termination region of the second conductivity type is an epitaxial layer, the first pillar and the third pillar each extend to a depth more than half of a thickness of the epitaxial layer. ### Claim 15 A termination structure, comprising: a conductive field plate; a plurality of pillars of a first conductivity type inside a termination region of a second conductivity type opposite the first conductivity type, the plurality of pillars defining a plurality of concentric rings surrounding an active area of a semiconductor device; a dielectric layer, the plurality of pillars including a first pillar coupled to the conductive field plate and including a second pillar disposed between first pillar included in the plurality of pillars and a third pillar included in the plurality of pillars, the second pillar included in the plurality of pillars being isolated from the conductive field plate by the dielectric layer, the dielectric layer being contiguous between the first pillar included in the plurality of pillars and the third pillar included in the plurality of pillars; a first mesa region disposed between the first pillar included in the plurality of pillars and the second pillar included in the plurality of pillars; and a second mesa region disposed between the second pillar included in the plurality of pillars and the third pillar included in the plurality of pillars, the first mesa region having a width greater than a width of the second mesa region. ### Claim 16 (depends on 15) The termination structure of claim 15, wherein the plurality of pillars are p-type pillars, the p-type pillars decrease in charge with distance from the active area such that a net n-type balance charge is formed in at least a portion of the termination region. ### Claim 17 (depends on 13) The apparatus of claim 13, further comprising: a first mesa region disposed between the first pillar included in the plurality of pillars and the second pillar included in the plurality of pillars; and a second mesa region disposed between the second pillar included in the plurality of pillars and the third pillar included in the plurality of pillars, the first mesa region having a width greater than a width of the second mesa region. ### Claim 18 (depends on 13) The apparatus of claim 13, wherein the second pillar is a last pillar from the plurality of pillars. ### Claim 19 (depends on 15) The termination structure of claim 15, wherein the plurality of pillars define a charge balance with the active area such that a breakdown voltage of the termination region is substantially equal to a breakdown voltage of the active area. ### Claim 20 (depends on 15) The termination structure of claim 15, wherein a distance between a pair of pillars from the plurality of pillars is approximately twice a distance between the plurality of pillars and an end of an active trench in the active area.