# US 8,786,032 B2 · P-type semiconductor device and method for manufacturing the same

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- Number: US 8,786,032 B2
- Document ID: US8786032B2
- Status: Granted
- Kind: B2
- Application number: 13/125,710
- Filed: 2011-02-27
- Published: 2013-04-25
- Granted: 2014-07-22
- Earliest claimed: 2010-07-16
- Assignees: Institute of Microelectronics, Chinese Academy of Sciences
- Applicants: Gaobo Xu; Qiuxia Xu
- Inventors: Gaobo Xu; Qiuxia Xu
- Web page: https://patentgrep.com/patent/US8786032B2

## CPC

- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present application provides a p-type semiconductor device and a method for manufacturing the same. The structure of the device comprises: a semiconductor substrate; a channel region positioned in the semiconductor substrate; a gate stack which is positioned on the channel region comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is positioned on the channel region and the gate electrode is positioned on the gate dielectric layer; and source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate; wherein the element Al is distributed in at least one of the upper surface, the bottom surface of the gate dielectric layer and the bottom surface of the gate electrode. The embodiments of the present invention are applicable for manufacturing MOSFET.

## Claims

### Claim 1

A p-type semiconductor device, comprising:
a semiconductor substrate;
a channel region positioned in the semiconductor substrate;
a gate stack, which is positioned on the channel region, comprising a gate dielectric layer and a gate electrode layer; wherein the gate dielectric layer is positioned on the channel region, and the gate electrode layer is positioned on the gate dielectric layer; and
source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate;
wherein the gate dielectric layer comprises a first dielectric layer and at least two second dielectric layers, the first dielectric layer being sandwiched between said two second dielectric layers, and
the first dielectric layer is a high k gate dielectric layer, and the second dielectric layers are oxide or nitride layers containing Al and are positioned above and below the first dielectric layer as upper and lower second dielectric layers, respectively, the element Al being distributed at an upper surface of the upper second dielectric layer and a bottom surface of the lower second dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the thickness of the second dielectric layers are 2-15 Å.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the element Al is distributed in any one of the surfaces in the form of Al—O electric dipoles.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein an oxide layer is further incorporated between the gate dielectric layer and the semiconductor substrate.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the second dielectric layers are AlOx or AlNx.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the high k gate dielectric layer contains Al.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the high k gate dielectric layer comprises: any one or a combination of several of HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, and HfTiON.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the gate electrode layer comprises a first metal layer, which is a metal nitride layer containing Al.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein the first metal layer comprises: any one or a combination of several of TaAlN, TiAlN, MoAlN and AlN.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, wherein the gate electrode layer further comprises a second metal layer positioned on the first metal layer.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein the second metal layer comprises Mo, W or the combination thereof.

### Claim 12 (depends on 10)

The semiconductor device according to claim 10, wherein the second metal layer comprises metal nitride.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein the metal nitride comprises: any one or a combination of several of TaN, TiN and MoN.