# US 8,786,030 B2 · Gate-last fabrication of quarter-gap MGHK FET

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- Number: US 8,786,030 B2
- Document ID: US8786030B2
- Status: Granted
- Kind: B2
- Application number: 13/570,388
- Filed: 2012-08-09
- Published: 2012-11-29
- Granted: 2014-07-22
- Earliest claimed: 2010-06-16
- Assignees: International Business Machines Corporation; Globalfoundries Inc.
- Applicants: Takashi Ando; Kisik Choi; Vijay Narayanan; Tenko Yamashita; Junli Wang
- Inventors: Takashi Ando; Kisik Choi; Vijay Narayanan; Tenko Yamashita; Junli Wang
- Web page: https://patentgrep.com/patent/US8786030B2

## CPC

- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

## Claims

### Claim 1

A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication, the quarter-gap NFET comprising:
a gate stack formed on a silicon substrate, the gate stack comprising:
a high-k dielectric layer located on the silicon substrate; and
a gate metal layer located over the high-k dielectric layer, the gate metal layer comprising titanium nitride and having the gate metal layer a thickness from about 30 angstroms to about 100 angstroms;
a threshold voltage tuning layer located between the high-k dielectric layer and the gate metal layer, wherein the threshold voltage tuning layer comprises a layer of lanthanum having a thickness from about 4 angstroms to 100 angstroms wherein the thickness of the threshold voltage tuning layer is based on a thickness of the gate metal layer; and
a metal contact formed over the gate stack,
wherein an effective work-function of the quarter-gap NFET is about 4.325 electron-volts.

### Claim 2 (depends on 1)

The quarter-gap NFET of claim 1, wherein the high-k dielectric layer comprises hafnium oxide, and the metal contact includes one of aluminum and tungsten.

### Claim 3

A mid-gap n-type field effect transistor (NFET) formed by gate-last fabrication, the mid-gap NFET comprising:
a gate stack formed on a silicon substrate, the gate stack comprising:
a high-k dielectric layer located on the silicon substrate; and
a first gate metal layer located over the high-k dielectric layer, the first gate metal layer comprising titanium nitride and having a thickness from about 20 angstroms to 35 angstroms;
a threshold voltage tuning layer located between the high-k dielectric layer and the first gate metal layer, wherein the threshold voltage tuning layer comprises aluminum and wherein a thickness of the threshold voltage tuning layer is based on the thickness of the first gate metal layer; and
a metal contact formed over the gate stack,
wherein an effective work-function of the mid-gap NFET is about 4.60 electron-volts.

### Claim 4 (depends on 3)

The mid-gap NFET of claim 3, wherein the high-k dielectric layer comprises hafnium oxide, and the metal contact comprises one of aluminum and tungsten.

### Claim 5 (depends on 3)

The mid-gap NFET of claim 3, wherein the gate stack further comprises an oxygen barrier layer located over the first gate metal layer, the oxygen barrier layer including tantalum nitride (TaN) formed by atomic layer deposition (ALD), and a second gate metal layer located over the oxygen barrier layer, wherein the first gate metal layer has a thickness of about 20 angstroms, and the second gate metal layer has a thickness from about 35 angstroms to about 100 angstroms.