# US 8,786,027 B2 · Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,786,027 B2
- Document ID: US8786027B2
- Status: Granted
- Kind: B2
- Application number: 13/886,373
- Filed: 2013-05-03
- Published: 2013-09-19
- Granted: 2014-07-22
- Earliest claimed: 2010-07-30
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Uwe Griebenow; Jan Hoentschel; Thilo Scheiper; Sven Beyer
- Web page: https://patentgrep.com/patent/US8786027B2

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/0278: {forming single crystalline channels on wafers after forming insulating device isolations}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/796: {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/01: Manufacture or treatment
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor region comprising an embedded strain-inducing semiconductor alloy formed at least partially in drain and source regions;
a gate electrode structure formed on a portion of said semiconductor region, said gate electrode structure comprising a metal-containing electrode material and a high-k dielectric material; and
contact areas formed above said strain-inducing semiconductor alloy and comprising a metal silicide having a top surface at a height that substantially corresponds to a height of a top surface of said metal-containing electrode material.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second semiconductor region comprising an embedded second strain-inducing semiconductor alloy formed at least partially in second drain and source regions; and
a second gate electrode structure formed on a portion of said second semiconductor region and comprising a second metal-containing electrode material and a second high-k dielectric material, wherein said embedded second strain-inducing semiconductor alloy differs from said embedded strain-inducing semiconductor alloy.

### Claim 3

A semiconductor device comprising:
a semiconductor region of a first transistor comprising a strain-inducing semiconductor alloy and a strained semiconductor material laterally enclosed by said strain-inducing semiconductor alloy, said strained semiconductor material and said strain-inducing semiconductor alloy differing in material composition; and
a gate electrode structure formed on a portion of said semiconductor region, said gate electrode structure comprising a metal-containing electrode material, a high-k dielectric material and a spacer structure that is aligned to said strained semiconductor material.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising:
a second semiconductor region of a second transistor comprising a second strain-inducing semiconductor alloy and a second strained semiconductor material laterally enclosed by said second strain-inducing semiconductor alloy, wherein said second semiconductor material and said second strain-inducing semiconductor material differ in material composition; and
a second gate electrode structure formed on a portion of said second semiconductor region, wherein said second gate electrode structure comprises a second metal-containing electrode material, a second high-k dielectric material and a second spacer structure that is aligned to said second strained semiconductor material.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein said strain-inducing semiconductor alloy is positioned at least partially in drain and source regions of said first transistor and said strained semiconductor material is positioned at least partially in a channel region of said first transistor.

### Claim 6 (depends on 3)

The semiconductor device of claim 3, wherein a bottom of said strained semiconductor material extends to a depth level in said semiconductor region that is below a depth level of a bottom of said strain-inducing semiconductor alloy.

### Claim 7 (depends on 3)

The semiconductor device of claim 3, wherein said semiconductor region comprises a semiconductor material layer that is positioned below said strain-inducing semiconductor alloy.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein said semiconductor material layer is positioned above a buried insulating material.

### Claim 9 (depends on 4)

The semiconductor device of claim 4, wherein said second strain-inducing semiconductor alloy is positioned at least partially in drain and source regions of said second transistor and said second strained semiconductor material is positioned at least partially in a channel region of said second transistor.

### Claim 10 (depends on 4)

The semiconductor device of claim 4, wherein a bottom of said second strained semiconductor material extends to a depth level in said second semiconductor region that is below a depth level of a bottom of said second strain-inducing semiconductor alloy.

### Claim 11 (depends on 4)

The semiconductor device of claim 4, wherein said strain-inducing semiconductor alloy comprises silicon and carbon and said second strain-inducing semiconductor alloy comprises silicon and germanium.

### Claim 12 (depends on 4)

The semiconductor device of claim 4, wherein said first transistor is an N-channel transistor and said second transistor is a P-channel transistor.

### Claim 13

A semiconductor device comprising:
an isolation structure laterally isolating an active region of said semiconductor device;
a plurality of transistor elements positioned in and above said active region, each of said plurality of transistor elements comprising a gate electrode structure that comprises a high-k gate dielectric material and a metal-containing electrode material; and
a plurality of material regions, each comprising:
a lower strain-inducing portion that is embedded in one of a source region and a drain region of a respective one of said plurality of transistor elements, said lower strain-inducing portion comprising a first semiconductor material; and
an upper contact portion that extends above said active region, said upper contact portion comprising a second semiconductor material and a metal silicide, wherein a height level of a top surface of said upper contact portion substantially corresponds to a height level of a top surface of said metal-containing electrode material.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein each of said plurality of transistor elements has a same conductivity type.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein a composition of said first semiconductor material is substantially the same as a composition of said second semiconductor material.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein said first and semiconductor materials comprise silicon and germanium.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein a germanium content of said first semiconductor material is greater than a germanium content of said second semiconductor material in at least part of said upper contact portion.

### Claim 18 (depends on 13)

The semiconductor device of claim 13, wherein said metal silicide is positioned at said top surface of said upper contact portion.

### Claim 19 (depends on 13)

The semiconductor device of claim 13, wherein said upper contact portion further comprises said high-k dielectric material and said metal containing electrode material.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein said metal-containing electrode material of said upper contact portion is positioned at said top surface of said upper contact portion.