# US 8,786,026 B2 · Optimized channel implant for a semiconductor device and method of forming the same

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- Number: US 8,786,026 B2
- Document ID: US8786026B2
- Status: Granted
- Kind: B2
- Application number: 13/029,626
- Filed: 2011-02-17
- Published: 2012-08-23
- Granted: 2014-07-22
- Earliest claimed: 2011-02-17
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Mukyeng Jung; No Young Chung; Kyung Woo Kim
- Inventors: Mukyeng Jung; No Young Chung; Kyung Woo Kim
- Web page: https://patentgrep.com/patent/US8786026B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10W 10/0148: {comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/0698: {Local interconnections}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device, comprising a substrate, a plurality of polysilicon portions formed on the substrate, wherein the polysilicon portions are spaced apart from each other, a plurality of source/drain regions formed in the substrate between adjacent polysilicon portions, and a dielectric layer formed on the polysilicon portions and on the source/drain regions, wherein the dielectric layer includes a cavity filled with conductive material to form a contact area, the contact area overlapping part of a source/drain region and part of a polysilicon portion to electrically connect the polysilicon portion with the source/drain region, and wherein part of the contact area extends below an upper surface of the substrate to contact an implant region with the same doping as the source/drain region. The implant region is next to the source/drain region and includes part of a channel region in the substrate under the polysilicon portion.

## Claims

### Claim 1

A semiconductor device, comprising:
a silicon trace doped with a first dopant;
an isolation region formed in the silicon trace;
a first polysilicon trace formed on the silicon trace;
a second polysilicon trace adjacent to the first polysilicon trace and formed on the silicon trace and the isolation region;
a source/drain region formed in the silicon trace between the first and the second polysilicon traces, wherein the source/drain region is doped with a second dopant opposite the first dopant;
a channel region in the silicon trace under the first polysilicon trace and doped with the first dopant;
a doping region formed in the silicon trace and between the source/drain region and the isolation region, wherein the doping region is doped with the second dopant and is partially overlapped by the second polysilicon trace; and
a dielectric layer formed on the first and second polysilicon traces and on the source/drain region, wherein the dielectric layer includes a cavity filled with a conductive material to form a contact area, the contact area overlapping part of the source/drain region and the second polysilicon trace to electrically connect the second polysilicon trace with the source/drain region.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein part of the contact area extends below an upper surface of the silicon trace to electrically connect the doping region to the source/drain region.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the contact area is a contact area of a rectangle structure.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the conductive material includes tungsten.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising another dielectric layer formed on the dielectric layer, wherein both dielectric layers include the cavity.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further comprising a silicide layer formed below an upper surface of the silicon trace in the source/drain region.

### Claim 7 (depends on 1)

A computer system comprising the semiconductor device of claim 1, wherein the computer system is one of a personal computer (PC), a personal digital assistant (PDA), an MP3 player, a digital audio recorder, a pen-shaped computer, a digital camera, or a video recorder.

### Claim 8

A system for transmitting or receiving data, the system comprising:
a memory device for storing a program; and
a processor in communication with the memory device,
wherein the memory device comprises:
a silicon trace doped with a first dopant;
an isolation region formed in the silicon trace;
a first polysilicon trace formed on the silicon trace;
a second polysilicon trace adjacent to the first polysilicon trace and formed on the silicon trace and the isolation region;
a source/drain region formed in the silicon trace between the first and the second polysilicon traces, wherein the source/drain region is doped with a second dopant opposite the first dopant;
a channel region in the silicon trace under the first polysilicon trace and doped with the first dopant;
a doping region formed in the silicon trace and between the source/drain region and the isolation region, wherein the doping region is doped with the second dopant and is partially overlapped by the second polysilicon trace; and
a dielectric layer formed on the first and second polysilicon traces and on the source/drain region,
wherein the dielectric layer includes a cavity filled with a conductive material to form a contact area, the contact area overlapping part of the source/drain region and the second polysilicon trace to electrically connect the second polysilicon trace with the source/drain region.

### Claim 9 (depends on 8)

The system according to claim 8, wherein the doping region is next to the source/drain region and includes part of a channel region in the substrate under the second polysilicon trace.

### Claim 10 (depends on 8)

The system according to claim 8, wherein the system comprises at least one of a mobile system, a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card.

### Claim 11

A semiconductor memory card, comprising:
an interface part that interfaces with an external device;
a controller that communicates with the interface part and a memory device via address and data buses, wherein the memory device comprises:
a silicon trace doped with a first dopant;
an isolation region formed in the silicon trace;
a first polysilicon trace formed on the silicon trace;
a second polysilicon trace adjacent to the first polysilicon trace and formed on the silicon trace and the isolation region;
a source/drain region formed in the silicon trace between the first and the second polysilicon traces wherein the source/drain region is doped with a second dopant opposite the first dopant;
a channel region in the silicon trace under the first polysilicon trace and doped with the first dopant;
a doping region formed in the silicon trace and between the source/drain region and the isolation region, wherein the doping region is doped with the second dopant and is partially overlapped by the second polysilicon trace; and
a dielectric layer formed on the first and second polysilicon traces and on the source/drain region, wherein the dielectric layer includes a cavity filled with a conductive material to form a contact area, the contact area overlapping part of the source/drain region and the second polysilicon trace to electrically connect the second polysilicon trace with the source/drain region.