# US 8,786,023 B2 · Embedded non-volatile memory

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- Number: US 8,786,023 B2
- Document ID: US8786023B2
- Status: Granted
- Kind: B2
- Application number: 13/707,895
- Filed: 2012-12-07
- Published: 2014-06-12
- Granted: 2014-07-22
- Earliest claimed: 2011-12-08
- Assignees: Contour Semiconductor, Inc.
- Applicants: Contour Semiconductor, Inc.
- Inventors: Daniel R. Shepard; Mac D. Apodaca; Thomas Michael Trent; James Juen Hsu
- Web page: https://patentgrep.com/patent/US8786023B2

## CPC

- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 84/0165: {the components including complementary IGFETs, e.g. CMOS devices}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/881: {Switching materials}
- H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The present invention is a method of incorporating a non-volatile memory into a CMOS process that requires four or fewer masks and limited additional processing steps. The present invention is an epi-silicon or poly-silicon process sequence that is introduced into a standard CMOS process (i) after the MOS transistors' gate oxide is formed and the gate poly-silicon is deposited (thereby protecting the delicate surface areas of the MOS transistors) and (ii) before the salicided contacts to those MOS transistors are formed (thereby performing any newly introduced steps having an elevated temperature, such as any epi-silicon or poly-silicon deposition for the formation of diodes, prior to the formation of that salicide). A 4F2 memory array is achieved with a diode matrix wherein the diodes are formed in the vertical orientation.

## Claims

### Claim 1

A CMOS logic device comprising MOS transistor logic and one or more diode memory arrays whereby the material to form the diodes of the memory array is deposited or grown after the MOS transistor gate material is deposited and before the annealing of any silicide in the MOS transistor contacts, and further comprising cups that are filled with a material that performs the function of an information storage element.

### Claim 2 (depends on 1)

The CMOS logic device of claim 1 whereby the material to form the diodes of the memory array is epi-silicon.

### Claim 3 (depends on 1)

The CMOS logic device of claim 1 whereby the material to form the diodes of the memory array is poly-silicon.

### Claim 4 (depends on 1)

The CMOS logic device of claim 1 whereby the material that performs the function of an information storage element is a phase-change material.

### Claim 5 (depends on 4)

The CMOS logic device of claim 4 whereby the phase-change material comprises a Chalcogenide alloy.

### Claim 6 (depends on 4)

The CMOS logic device of claim 4 whereby the phase-change material comprises one or more of the elements Germanium, Tellurium or Antimony.

### Claim 7 (depends on 1)

The CMOS logic device of claim 1 further comprising contacts between the silicon on the substrate and one or more metal layers formed above the substrate.

### Claim 8 (depends on 7)

The CMOS logic device of claim 7 whereby the cups are formed by the selective removal of said contacts.

### Claim 9

An electronic system comprising a memory device whereby the memory device comprises MOS transistor logic and one or more diode memory arrays whereby the material to form the diodes of the memory array is deposited or grown after the MOS transistor gate material is deposited and before the annealing of any silicide in the MOS transistor contacts, and whereby the diodes of the memory array are comprised by information storage cells that also comprise cups that are filled with a material that performs the function of an information storage element.

### Claim 10 (depends on 9)

The electronic system of claim 9 whereby the material to form the diodes of the memory array is epi-silicon.

### Claim 11 (depends on 9)

The electronic system of claim 9 whereby the material to form the diodes of the memory array is poly-silicon.

### Claim 12 (depends on 9)

The electronic system of claim 9 whereby the material that performs the function of an information storage element is a phase-change material.

### Claim 13 (depends on 12)

The electronic system of claim 12 whereby the phase-change material comprises a Chalcogenide alloy.

### Claim 14 (depends on 12)

The electronic system of claim 12 whereby the phase-change material comprises one or more of the elements Germanium, Tellurium or Antimony.

### Claim 15 (depends on 9)

The electronic system of claim 9 further comprising contacts between the silicon on the substrate and one or more metal layers formed above the substrate.

### Claim 16 (depends on 15)

The electronic system of claim 15 whereby the cups are formed by the selective removal of said contacts.

### Claim 17 (depends on 9)

The electronic system of claim 9 whereby the memory device is comprised by a package that is removable.

### Claim 18 (depends on 9)

The electronic system of claim 9 whereby the memory device contains one or more types of information selected from the list of digital text, digital books, digital music, digital audio, digital photography, digital video, and digital cartography.

### Claim 19

An electronic system comprising a memory device whereby the memory device comprises MOS transistor logic and one or more diode memory arrays whereby the material to form the diodes of the memory array is deposited or grown after the MOS transistor gate material is deposited and before the annealing of any silicide in the MOS transistor contacts, and further comprising (i) contacts between the silicon on the substrate and one or more metal layers formed above the substrate and (ii) cups formed by the selective removal of said contacts.

### Claim 20 (depends on 19)

The electronic system of claim 19 whereby the material to form the diodes of the memory array is epi-silicon.

### Claim 21 (depends on 19)

The electronic system of claim 19 whereby the material to form the diodes of the memory array is poly-silicon.

### Claim 22 (depends on 19)

The electronic system of claim 19 whereby the memory device is comprised by a package that is removable.

### Claim 23 (depends on 19)

The electronic system of claim 19 whereby the memory device contains one or more types of information selected from the list of digital text, digital books, digital music, digital audio, digital photography, digital video, and digital cartography.