# US 8,786,021 B2 · Semiconductor structure having an active device and method for manufacturing and manipulating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,021 B2 - Document ID: US8786021B2 - Status: Granted - Kind: B2 - Application number: 13/603,333 - Filed: 2012-09-04 - Published: 2014-03-06 - Granted: 2014-07-22 - Earliest claimed: 2012-09-04 - Assignees: Macronix International Co., Ltd. - Applicants: Wing-Chor Chan; Li-Fan Chen - Inventors: Wing-Chor Chan; Li-Fan Chen - Web page: https://patentgrep.com/patent/US8786021B2 ## CPC - H10D 1/47: Resistors having no potential barriers - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 30/83: FETs having PN junction gate electrodes - H10D 84/0126: {the components including insulated gates, e.g. IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/151: {LDMOS having built-in components} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10N 79/00: Integrated devices, or assemblies of multiple devices, comprising at least one solid-state element covered by group H10N70/00 (ReRAM devices H10B63/00; PCRAM devices H10B63/10) - H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures} - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 62/157: {Impurity concentrations or distributions} - H10D 62/357: {of FETs} - H10D 62/378: {Contact regions to the substrate regions} - H10D 64/516: {the thicknesses being non-uniform} - H10D 89/811: {using FETs as protective elements} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A semiconductor structure comprising a substrate, an active device, a field oxide layer and a poly-silicon resistor is disclosed. The active device is formed in a surface area of the substrate. The active device has a first doped area, a second doped area and a third doped area. The second doped area is disposed on the first doped area. The first doped area is between the second and the third doped areas. The first doped area has a first type conductivity. The third doped area has a second type conductivity. The first and the second type conductivities are different. The field oxide layer is disposed on a part of the third doped area. The poly-silicon resistor is disposed on the field oxide layer and is electrically connected to the third doped area. ## Claims ### Claim 1 A semiconductor structure, comprising: a substrate; an active device, formed in a surface area of the substrate, the active device having a first doped area, a second doped area and a third doped area, wherein the second doped area is disposed on the first doped area, the first doped area is disposed between the second and the third doped area, the first doped area has a first type conductivity, the third doped area has a second type conductivity and a drain, the first type conductivity and the second type conductivity are different; a field oxide layer, disposed on a part of the third doped area; and a poly-silicon resistor, disposed on the field oxide layer and electrically connected to the third doped area and coupled to a ground terminal, wherein the poly-silicon resistor comprising at least three electrical connecting terminals, the at least three electrical connecting terminals coupled to the drain, an internal circuit and the ground terminal, respectively. ### Claim 2 (depends on 1) A semiconductor structure according to claim 1, wherein the first doped area comprises a first light doped area having the first type conductivity, the second doped area is a first heavily doped area having one of the first and the second type conductivities, and the third doped area comprises a second light doped area and a second heavily doped area, the second light doped area and the second heavily doped area have the second type conductivity. ### Claim 3 (depends on 1) A semiconductor structure according to claim 1, wherein the poly-silicon resistor is electrically connected to an internal circuit and a ground terminal, the poly-silicon resistor has a plurality of half-circular structures, a plurality of elliptical structures, a plurality of irregular semicircle structures, a plurality of concentric circle structures or a plurality of octagon structures. ### Claim 4 (depends on 3) A semiconductor structure according to claim 3, wherein the second heavily doped area is the drain, the half-circular structures, the elliptical structures, the irregular semicircle structures, the concentric circle structures or the octagon structures encircle the drain. ### Claim 5 (depends on 4) A semiconductor structure according to claim 4, wherein the half-circular structures, the elliptical structures or the concentric circle structures comprise a plurality of ring-shaped structures with different curvatures. ### Claim 6 (depends on 4) A semiconductor structure according to claim 4, wherein the half-circular structures comprise a plurality of first concentric half rings with different radius and a plurality of second concentric half rings with different radius, the first and the second half rings are symmetrically disposed or mirror-imaged disposed relatively to the drain, two neighboring half rings of the first half rings are electrically connected, and two neighboring half rings of the second half rings are electrically connected. ### Claim 7 (depends on 6) A semiconductor structure according to claim 6, wherein the two neighboring first half rings and the two neighboring second half rings are electrically connected by a metal material or a poly-silicon material. ### Claim 8 (depends on 1) A semiconductor structure according to claim 1, further comprising a plurality of buried layers disposed between the first doped area and the substrate, wherein the buried layers has a second type conductivity, and a distance between two of the buried layers is related to a pinch-off voltage of the active device. ### Claim 9 (depends on 1) A semiconductor structure according to claim 1, further comprising a plurality of fourth doped areas disposed adjacent to the first doped area, wherein the fourth doped areas have the second type conductivity, and a distance between the fourth doped areas is related the a pinch-off voltage of the active device. ### Claim 10 (depends on 9) A semiconductor structure according to claim 9, wherein the second doped area is coupled to a gate voltage, and a part of the fourth doped areas is coupled to a source voltage.