# US 8,786,020 B2 · Method of fabricating a semiconductor device including a gate having a plurality of fingers extended over a plurality of isolation regions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,020 B2 - Document ID: US8786020B2 - Status: Granted - Kind: B2 - Application number: 13/543,731 - Filed: 2012-07-06 - Published: 2012-11-01 - Granted: 2014-07-22 - Earliest claimed: 2009-12-18 - Assignees: Intel Corporation - Applicants: Michael Andrew Smith - Inventors: Michael Andrew Smith - Web page: https://patentgrep.com/patent/US8786020B2 ## CPC - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate} - H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability} - H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)} - H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]} - H10D 30/65: Lateral DMOS [LDMOS] FETs - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 64/111: {Field plates} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments of the present invention describe a semiconductor device implementing the reduced-surface-field (RESURF) effect. The semiconductor device comprises a source/drain region having a plurality of isolation regions interleaved with source/drain extension regions. A gate electrode is formed on the semiconductor device, where the gate electrode includes gate finger elements formed over the isolation regions to induce capacitive coupling. The gate finger elements enhance the depletion of the source/drain extension regions, thus inducing a higher breakdown voltage. ## Claims ### Claim 1 A semiconductor device comprising: a substrate having a channel region between a source region and a drain region; a first plurality of isolation regions that interleave a plurality of drain extension regions in the drain region; and a gate electrode having a first region formed over the channel region, a second region formed directly on a top surface of the first region, and a first plurality of finger elements formed over the first plurality of isolation regions, wherein each isolation region has at least one overlying finger element. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the second region comprises a center portion formed directly on the top surface and the sidewalls of the first region, and wherein the first plurality of finger elements extend from the center portion of the second region. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein the bottom surfaces of the first plurality of finger elements are substantially coplanar with the bottom surface of the first region. ### Claim 4 (depends on 2) The semiconductor device of claim 2, wherein the top surfaces of the first plurality of finger elements are lower than the top surface of the center portion. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the first region comprises a center portion formed over the channel region. ### Claim 6 (depends on 5) The semiconductor device of claim 5, wherein the first plurality of finger elements extends from the center portion of the first region. ### Claim 7 (depends on 5) The semiconductor device of claim 5, wherein the first plurality of finger elements is separated from center portion of the first region. ### Claim 8 (depends on 5) The semiconductor device of claim 5, further comprising an insulating layer formed around the center portion of the first region, and formed between the first plurality of finger elements. ### Claim 9 (depends on 6) The semiconductor device of claim 6, wherein the second region is formed directly on the center portion of the first region and the first plurality of finger elements. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the first plurality of finger elements have substantially uniform width. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein the first plurality of finger elements have a smaller width than the first plurality of isolation regions. ### Claim 12 (depends on 2) The semiconductor device of claim 2, wherein the first plurality of finger elements have a tapered profile with decreasing width. ### Claim 13 A method of forming a semiconductor device comprising: forming an insulating region on a substrate, the insulating region comprising a gate oxide region and a plurality of isolation regions in a source or a drain region; forming a first poly layer over the gate oxide region, the first poly layer having a plurality of gate finger elements extended over the plurality of isolation regions; depositing an insulating layer over the first poly layer; polishing the insulating layer so that the top surface of the insulating layer is substantially coplanar with the top surface of the first poly layer; and depositing a second poly layer over the first poly layer. ### Claim 14 (depends on 13) The method of claim 13, wherein forming the insulating region comprises using thermal oxidation to grow the gate oxide region and the plurality of isolation regions. ### Claim 15 (depends on 13) The method of claim 13, wherein forming the first poly layer comprises: depositing a poly film on the insulating region; and etching the poly film to define the first poly layer including the plurality of gate finger elements. ### Claim 16 (depends on 13) The method of claim 13, wherein forming the second poly layer over the first poly layer further comprises etching the second poly layer so that the sidewalls of the second poly layer are aligned to the tip edges of the plurality of isolation regions.