# US 8,786,018 B2 · Self-aligned carbon nanostructure field effect transistors using selective dielectric deposition

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- Number: US 8,786,018 B2
- Document ID: US8786018B2
- Status: Granted
- Kind: B2
- Application number: 13/610,158
- Filed: 2012-09-11
- Published: 2014-03-13
- Granted: 2014-07-22
- Earliest claimed: 2012-09-11
- Assignees: International Business Machines Corporation
- Applicants: Damon B. Farmer; Aaron D. Franklin; Shu-Jen Han; George S. Tulevski
- Inventors: Damon B. Farmer; Aaron D. Franklin; Shu-Jen Han; George S. Tulevski
- Web page: https://patentgrep.com/patent/US8786018B2

## CPC

- H10D 30/6732: {Bottom-gate only TFTs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6746: {Amorphous silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10K 85/221: {Carbon nanotubes}
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/121: {oriented parallel to substrates}
- H10K 10/468: {characterised by the gate dielectrics}
- Y10S 977/742: Carbon nanotubes, CNTs
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

Self-aligned carbon nanostructure field effect transistor structures are provided, which are formed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.

## Claims

### Claim 1

A transistor device, comprising:
an insulating layer;
gate electrode embedded in the insulating layer;
a dielectric deposition-prohibiting layer formed on a surface of the insulating layer surrounding the gate electrode;
a gate dielectric layer selectively formed on the gate electrode, wherein the gate dielectric layer comprises a first dielectric material;
a channel structure comprising a carbon nanostructure disposed on the gate dielectric layer;
a passivation layer selectively formed on the gate dielectric layer, covering a portion of the channel structure that is disposed on the gate dielectric layer, wherein the passivation layer comprises a second dielectric material; and
source and drain contacts formed on opposing sides of the passivation layer in contact with the channel structure,
wherein the dielectric deposition-prohibiting layer comprises a material that prevents chemical reactive deposition of the first and second dielectric materials on top of exposed portions of the dielectric deposition-prohibiting layer surrounding the gate electrode when the gate dielectric layer and passivation layer are selectively formed by the chemical reactive deposition of the first and second dielectric materials.

### Claim 2 (depends on 1)

The device of claim 1, wherein the dielectric deposition-prohibiting layer comprises a graphene layer.

### Claim 3 (depends on 1)

The device of claim 1, wherein the dielectric deposition-prohibiting layer comprises a molecular self-assembled monolayer.

### Claim 4 (depends on 1)

The device of claim 1, wherein the dielectric deposition-prohibiting layer comprises a hydrophobic monolayer.

### Claim 5 (depends on 1)

The device of claim 1, wherein the carbon nanostructure comprises a carbon nanotube.

### Claim 6 (depends on 1)

The device of claim 1, wherein the passivation layer has sloped sidewalls.

### Claim 7 (depends on 1)

The device of claim 1, wherein the channel structure comprises extended portions that extend past opposing sides of the gate dielectric layer and gate electrode.

### Claim 8 (depends on 7)

The device of claim 7, wherein the extended portions of the channel structure are embedded in the source and drain contacts.

### Claim 9

An integrated circuit, comprising a substrate, and a transistor device formed on the substrate, wherein the transistor device comprises:
an insulating layer;
gate electrode embedded in the insulating layer;
a dielectric deposition-prohibiting layer formed on a surface of the insulating layer surrounding the gate electrode;
a gate dielectric layer selectively formed on the gate electrode, wherein the gate dielectric layer comprises a first dielectric material;
a channel structure comprising a carbon nanostructure disposed on the gate dielectric layer;
a passivation layer selectively formed on the gate dielectric layer, covering a portion of the channel structure that is disposed on the gate dielectric layer, wherein the passivation layer comprises a second dielectric material; and
source and drain contacts formed on opposing sides of the passivation layer in contact with the channel structure,
wherein the dielectric deposition-prohibiting layer comprises a material that prevents chemical reactive deposition of the first and second dielectric materials on top of exposed portions of the dielectric deposition-prohibiting layer surrounding the gate electrode when the gate dielectric layer and passivation layer are selectively formed by the chemical reactive deposition of the first and second dielectric materials.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, wherein the dielectric deposition-prohibiting layer comprises a graphene layer.

### Claim 11 (depends on 9)

The integrated circuit of claim 9, wherein the dielectric deposition-prohibiting layer comprises a molecular self-assembled monolayer.

### Claim 12 (depends on 9)

The integrated circuit of claim 9, wherein the dielectric deposition-prohibiting layer comprises a hydrophobic monolayer.

### Claim 13 (depends on 9)

The integrated circuit of claim 9, wherein the carbon nanostructure comprises a carbon nanotube.

### Claim 14 (depends on 9)

The integrated circuit of claim 9, wherein the passivation layer has sloped sidewalls.

### Claim 15 (depends on 9)

The integrated circuit of claim 9, wherein the channel structure comprises extended portions that extend past opposing sides of the gate dielectric layer and gate electrode.

### Claim 16 (depends on 15)

The integrated circuit of claim 15, wherein the extended portions of the channel structure are embedded in the source and drain contacts.

### Claim 17 (depends on 1)

The device of claim 1, wherein the first dielectric material and the second dielectric material are different dielectric materials.

### Claim 18 (depends on 1)

The device of claim 1, wherein the first dielectric material and the second dielectric material are the same dielectric materials.

### Claim 19 (depends on 9)

The integrated circuit of claim 9, wherein the first dielectric material and the second dielectric material are different dielectric materials.

### Claim 20 (depends on 9)

The integrated circuit of claim 9, wherein the first dielectric material and the second dielectric material are the same dielectric materials.