# US 8,786,017 B2 · Strained Ge-on-insulator structure and method for forming the same

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- Number: US 8,786,017 B2
- Document ID: US8786017B2
- Status: Granted
- Kind: B2
- Application number: 13/263,222
- Filed: 2011-08-25
- Published: 2012-09-13
- Granted: 2014-07-22
- Earliest claimed: 2011-03-10
- Assignees: Tsinghua University
- Applicants: Jing Wang; Jun Xu; Lei Guo
- Inventors: Jing Wang; Jun Xu; Lei Guo
- Web page: https://patentgrep.com/patent/US8786017B2

## CPC

- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10P 90/1906: {Preparing SOI wafers}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/795: {being in lateral device isolation regions, e.g. STI}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/01356: {the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence)}
- H10P 90/1914: {using bonding}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a plurality of shallow trench isolation structures extending into the silicon substrate and filled with an insulating dielectric material to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.

## Claims

### Claim 1

A strained Ge-on-insulator structure, comprising:
a silicon substrate, wherein an oxide insulating layer is formed on a surface of the silicon substrate;
a Ge layer formed on the oxide insulating layer, wherein a first passivation layer is directly formed on the oxide insulating layer, the Ge layer is directly formed on the first passivation layer, and the first passivation layer is a strontium germanide layer, a barium germanide layer, or a stannum germanide layer;
a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and
a plurality of shallow trench isolation structures extending into the silicon substrate and filled with an insulating dielectric material to produce a strain in the channel region.

### Claim 2 (depends on 1)

The strained Ge-on-insulator structure according to claim 1, further comprising:
a second passivation layer formed on the Ge layer,
wherein the second passivation layer is a strontium germanide layer, a barium germanide layer, or a stannum germanide layer.

### Claim 3 (depends on 1)

The strained Ge-on-insulator structure according to claim 1, further comprising:
a second passivation layer formed on the Ge layer,
wherein the second passivation layer is a SiyGe1-y layer, in which y is within a range from 0 to 1.

### Claim 4 (depends on 1)

The strained Ge-on-insulator structure according to claim 1, wherein the insulating dielectric material is silicon nitride.

### Claim 5 (depends on 1)

The strained Ge-on-insulator structure according to claim 1, further comprising:
a SiN stress cap layer covering the gate stack to produce a strain in the channel region.

### Claim 6 (depends on 1)

The strained Ge-on-insulator structure according to claim 1, wherein the source and the drain are a SixGe1-x:C source and a SixGe1-x:C drain respectively 5 to produce a corresponding strain in the channel region, in which x is within a range from 0 to 1 and a content of C is within a range from 0 to 7.5%.