# US 8,786,013 B2 · Trench transistor

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- Number: US 8,786,013 B2
- Document ID: US8786013B2
- Status: Granted
- Kind: B2
- Application number: 13/939,166
- Filed: 2013-07-10
- Published: 2013-11-07
- Granted: 2014-07-22
- Earliest claimed: 2011-09-21
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: Globalfoundries Singapore Pte. Ltd.
- Inventors: Shajan Mathew; Purakh Raj Verma
- Web page: https://patentgrep.com/patent/US8786013B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/0289: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/658: {having trench gate electrodes}
- H10D 62/158: {Dispositions}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a device is disclosed. A substrate defined with a device region is provided. A buried doped region is formed in the substrate in the device region. A gate is formed in a trench in the substrate in the device region. A channel of the device is disposed on a sidewall of the trench. The buried doped region is disposed below the gate. A distance from the buried doped region to the channel is a drift length LD of the device. A surface doped region is formed adjacent to the gate.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate defined with a device region;
a buried heavily doped drain region in the substrate in the device region;
a gate in a trench in the device region, wherein a channel of the device is disposed on a sidewall of the trench, the buried heavily doped drain region is disposed below the gate and is vertically and laterally displaced away from the channel of the device, wherein a distance from the buried heavily doped drain region to the channel is a drift length LD of the device;
a drain connector disposed in the trench and is connected to the buried heavily doped drain region, wherein the drain connector is isolated from the gate; and
a surface heavily doped region adjacent to the gate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1 wherein the device region is surrounded by device isolation region.

### Claim 3 (depends on 2)

The semiconductor device of claim 2 wherein the device region comprises one or more internal device regions, dividing the device region into multiple device sub-regions.

### Claim 4 (depends on 1)

The semiconductor device of claim 1 wherein the device region comprises:
a first device doped well; and
a second device doped well, the second device doped well has a depth equals to a channel length LC of the channel,
wherein the first device doped well has a depth greater than the second device doped well.

### Claim 5 (depends on 4)

The semiconductor device of claim 4 wherein the first device doped well comprises first polarity type dopants and the second device doped well comprises second polarity type dopants.

### Claim 6 (depends on 5)

The semiconductor device of claim 5 wherein the second device doped well is disposed substantially within the first device doped well.

### Claim 7

The semiconductor device of 6 wherein:
the trench is disposed in the first and second device doped wells and the trench comprises first and second portions.

### Claim 8 (depends on 7)

The semiconductor device of claim 7 comprising:
the first portion of the trench has a depth greater than an interface of the first and second device doped wells;
gate insulators disposed on either sides of the drain connector in the first portion of the trench; and
gate electrodes on either sides of the gate insulators in the first portion of the trench.

### Claim 9

A semiconductor device comprising:
a substrate defined with a device region;
a buried heavily doped drain region in the substrate in the device region;
a gate in a trench in the device region, wherein a channel of the device is disposed on a sidewall of the trench, the buried heavily doped drain region is disposed below the gate and is vertically and laterally displaced away from the channel of the device, wherein a distance from the buried heavily doped drain region to the channel is a drift length LD of the device;
a drain connector disposed in the trench and is connected to the buried heavily doped drain region, wherein the drain connector is isolated from the gate;
a gate dielectric layer which lines sidewalls and bottom of a first portion of the trench without lining sidewalls of the drain connector; and
a surface heavily doped region adjacent to the gate.

### Claim 10 (depends on 8)

The semiconductor device of claim 8 wherein each of the gate insulators include a primary gate insulator and a secondary gate insulator which comprise different materials.

### Claim 11

A semiconductor device comprising:
a substrate defined with a device region;
first and second device doped wells in the device region, wherein the first device doped well has a depth greater than the second device doped well;
a buried heavily doped region which is disposed within the first device doped well;
a gate in a trench in the device region, the trench has a depth greater than an interface of the first and second device doped wells, wherein a channel of the device is disposed on a sidewall of the trench, the buried heavily doped region is disposed below the gate and is vertically and laterally displaced away from the gate and channel of the device, wherein a distance from the buried heavily doped region to the channel is a drift length LD of the device;
a drain connector disposed in the trench, wherein the drain connector is disposed adjacent to the gate and extends from a top surface of the substrate to the buried heavily doped region;
a gate dielectric layer which lines sidewalls and bottom of the trench without lining sidewalls of the drain connector; and
a surface heavily doped region adjacent to the gate.

### Claim 12 (depends on 11)

The semiconductor device of claim 11 wherein the second device doped well has a depth equals to a channel length LC of the channel.

### Claim 13 (depends on 11)

The semiconductor device of claim 11 wherein the first device doped well comprises first polarity type dopants and the second device doped well comprises second polarity type dopants and the first and second device doped wells comprise dopant concentration lesser than the buried and surface heavily doped regions.

### Claim 14 (depends on 11)

The semiconductor of claim 11 wherein the drain connector directly contacts the buried heavily doped region.

### Claim 15 (depends on 14)

The semiconductor device of claim 14 wherein the buried heavily doped region is disposed directly below the drain connector and occupies a portion of the first device doped well.

### Claim 16 (depends on 11)

The semiconductor device of claim 11 comprising:
gate insulators disposed on either sides of the drain connector in the trench; and
gate electrodes on either sides of the gate insulators in the trench.

### Claim 17 (depends on 16)

The semiconductor device of claim 16 wherein each of the gate insulators include a primary gate insulator and a secondary gate insulator which comprise different materials.

### Claim 18 (depends on 11)

The semiconductor device of claim 11 wherein the gate dielectric layer comprises the same thickness.