# US 8,786,012 B2 · Power semiconductor device and a method for forming a semiconductor device

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- Number: US 8,786,012 B2
- Document ID: US8786012B2
- Status: Granted
- Kind: B2
- Application number: 13/542,737
- Filed: 2012-07-06
- Published: 2012-11-15
- Granted: 2014-07-22
- Earliest claimed: 2010-07-26
- Assignees: Infineon Technologies Austria AG
- Applicants: Anton Mauder; Franz Hirler; Wolfgang Lehnert; Rudolf Berger; Klemens Pruegl; Hans-Joachim Schulze; Helmut Strack
- Inventors: Anton Mauder; Franz Hirler; Wolfgang Lehnert; Rudolf Berger; Klemens Pruegl; Hans-Joachim Schulze; Helmut Strack
- Web page: https://patentgrep.com/patent/US8786012B2

## CPC

- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 8/411: {PN diodes having planar bodies}
- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 12/421: {on insulating layers or insulating substrates, e.g. thin-film IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 64/118: {Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/68: characterised by the insulator, e.g. by the gate insulator
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 84/141: {VDMOS having built-in components}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/66: {characterised by the type of materials}
- H10P 14/6929: {the material containing aluminium, e.g. AlSiOx}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/8325: {Silicon carbide}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/111: {Field plates}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A power semiconductor device has a semiconductor body which includes an active area and a peripheral area which both define a horizontal main surface of the semiconductor body. The semiconductor body further includes an n-type semiconductor layer, a pn junction and at least one trench. The n-type semiconductor layer is embedded in the semiconductor body and extends to the main surface in the peripheral area. The pn junction is arranged between the n-type semiconductor layer and the main surface in the active area. The at least one trench extends in the peripheral area from the main surface into the n-type semiconductor layer and includes a dielectric layer with fixed negative charges. In the vertical direction, the dielectric layer is arranged both below and above the pn junction. The dielectric layer with fixed negative charges typically has a negative net charge. Further, a method for forming a semiconductor device is provided.

## Claims

### Claim 1

A power semiconductor device comprising:
a semiconductor body comprising:
an active area and a peripheral area which both define a horizontal main surface of the semiconductor body, wherein the peripheral area forms an edge of the semiconductor body;
an n-type semiconductor layer which is beneath the main surface in the active area and extends to the main surface in the peripheral area;
a pn junction which is arranged between the n-type semiconductor layer and the main surface in the active area; and
at least one trench which extends in the peripheral area from the main surface into the n-type semiconductor layer and comprises a dielectric layer comprising fixed negative charges and being, in a vertical direction which is substantially perpendicular to the main surface, arranged both below and above the pn junction.

### Claim 2 (depends on 1)

The power semiconductor device of claim 1, wherein a charge carrier density per area of the fixed negative charges of the dielectric layer decreases step-wise or continuously with increasing distance from the main surface.

### Claim 3 (depends on 1)

The power semiconductor device of claim 1, wherein the dielectric layer comprises an aluminum-doped silicon oxide and/or an aluminum-doped oxynitride.

### Claim 4 (depends on 1)

The power semiconductor device of claim 1, wherein the at least one trench comprises a cavity.

### Claim 5 (depends on 1)

The power semiconductor device claim 1, wherein the pn junction adjoins the dielectric layer.

### Claim 6 (depends on 1)

The power semiconductor device of claim 1, wherein the dielectric layer has a negative net charge, the power semiconductor device further comprising a further trench which extends in the peripheral area from the main surface into the n-type semiconductor layer and comprises a further dielectric layer having a positive net charge, the further dielectric layer, in the vertical direction, being arranged both below and above the pn junction.

### Claim 7 (depends on 6)

The power semiconductor device of claim 6, wherein at least one portion of the at least one trench and/or a portion of the further trench forms an acute angle with the active area.

### Claim 8

A vertical semiconductor transistor, comprising:
a semiconductor body comprising:
a first n-type semiconductor region;
a second semiconductor region which forms a pn junction with the first semiconductor region;
a third semiconductor region; and
a dielectric layer which comprises fixed negative charges in at least one portion, adjoins the second semiconductor region and is arranged between the first semiconductor region and the third semiconductor region; and
an insulated gate electrode adjacent to the first semiconductor region and the second semiconductor region and separated from the dielectric layer by the second semiconductor region.

### Claim 9 (depends on 8)

The vertical semiconductor transistor of claim 8, wherein the dielectric layer extends from a main surface of the semiconductor body into the semiconductor body, and wherein a charge carrier density per area of the fixed negative charges of the dielectric layer decreases step-wise or continuously with increasing distance from the main surface.

### Claim 10 (depends on 8)

The vertical semiconductor transistor of claim 8, wherein the dielectric layer comprises an aluminum-doped silicon oxide or an aluminum-doped oxynitride.

### Claim 11 (depends on 8)

The vertical semiconductor transistor of claim 8, wherein the vertical semiconductor transistor is a TEDFET, and wherein the dielectric layer forms an accumulation oxide.

### Claim 12 (depends on 8)

The vertical semiconductor transistor of claim 8, wherein the dielectric layer is arranged in a vertical trench which extends from a main surface of the semiconductor body to a back surface of the semiconductor body arranged opposite the main surface.

### Claim 13 (depends on 8)

The vertical semiconductor transistor of claim 8, wherein a charge carrier density per area of the fixed negative charges of the dielectric layer in a horizontal plane has a highest value approximately in a center region between the third semiconductor region and the first semiconductor region.

### Claim 14 (depends on 8)

The vertical semiconductor transistor of claim 8, wherein the dielectric layer has a negative net charge in the at least one portion, and wherein the dielectric layer has a positive net charge in at least one further portion.

### Claim 15 (depends on 8)

The vertical semiconductor transistor of claim 8, further comprising a further dielectric layer having a positive net charge, the further dielectric layer extending from a main surface of the semiconductor body into the semiconductor body.