# US 8,786,011 B2 · Semiconductor device

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- Number: US 8,786,011 B2
- Document ID: US8786011B2
- Status: Granted
- Kind: B2
- Application number: 13/643,468
- Filed: 2011-04-27
- Published: 2013-02-21
- Granted: 2014-07-22
- Earliest claimed: 2010-04-28
- Assignees: Nissan Motor Co., Ltd.
- Applicants: Shigeharu Yamagami; Tetsuya Hayashi; Tatsuhiro Suzuki
- Inventors: Shigeharu Yamagami; Tetsuya Hayashi; Tatsuhiro Suzuki
- Web page: https://patentgrep.com/patent/US8786011B2

## CPC

- H10D 84/035: {using silicon carbide [SiC] technology}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 8/60: Schottky-barrier diodes
- H10D 12/031: {of IGBTs}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/8325: {Silicon carbide}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/146: {the built-in components being Schottky barrier diodes}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 8/051: {of Schottky diodes}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/154: {Dispositions}
- H10D 62/8303: {Diamond}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/0115: {to silicon carbide}
- H10P 30/2042: {into crystalline silicon carbide}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Each insulating gate portion forms a channel in part of a first well region located between a drift region and source region. A first main electrode forms junctions with part of the drift region exposed in the major surface of the drift region to constitute unipolar diodes and is connected to the first well regions and the source regions. The plurality of insulating gate portions have linear patterns parallel to each other when viewed in the normal direction of the major surface. Between each pair of adjacent insulating gate portions, junction portions in which the first main electrode forms junctions with the drift region and the first well regions are arranged along the direction that the insulating gate portions extend. The channels are formed at least in the normal direction of the major surface.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a drift region of first conductivity type which is provided on the semiconductor substrate;
a plurality of first well regions of second conductivity type which are provided within the drift region and are partially exposed in a major surface of the drift region;
a plurality of source regions of the first conductivity type which are located within the first well regions and are partially exposed in the major surface;
three or more insulating gate portions which form channels reversed to the first conductivity type in part of the first well regions located between the drift region and source regions; and
a first main electrode which forms a contact with the drift region exposed in the major surface to constitute a unipolar diode and is connected to the first well regions and the source regions, wherein
the plurality of insulating gate portions have linear patterns parallel to each other when viewed in the normal direction of the major surface,
between each pair of adjacent insulating gate portions, the first well regions and junction portions in which the first main electrode forms junctions with the drift region are arranged along the direction that the insulating gate portions extend, and the first well regions and the junction portions in which the first main electrode form junctions with the drift region are arranged in line along a direction vertical to the direction that the insulating gate portions extend,
the channels are formed in the normal direction of the major surface and in the vertical direction to the normal of the major surface, and
a length of the channels formed in the vertical direction to the normal of the major surface is longer than a length of the channels formed in the normal direction of the major surface.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the first well regions are located on an upper part of the drift region, the source regions are located on an upper part of the first well regions, the first main electrode is located on the major surface of the drift region, and the distance between each source region and the drift region in the direction vertical to the normal of the major surface is longer than the distance between the source region and the drift region in the normal direction of the major surface.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein distance between each pair of the first well regions adjacent to each other along the direction that the insulating gate portions extend is set to a distance which allows depletion layers extending from edges of the pair of adjacent first well regions to the drift region to overlap each other when a predetermined voltage is applied across the drift region and the first main electrode in a direction opposite to a forward direction of the unipolar diode.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising a well contact region which is formed in part of each channel extending along the direction vertical to the normal of the major surface and has a higher concentration of impurities of the second conductivity type than that of the first well regions.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, further comprising a plurality of well contact regions of the second conductivity type which are located in places different from the source regions within the first well regions and are partially exposed in the major surface to be connected to the first main electrode, wherein
the plurality of well contact regions intersect with the direction that the insulating gate portions extend and have linear patterns parallel to each other.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the well contact regions are located at boundaries between the drift region and the first well regions.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, wherein the plurality of source regions have linear patterns which intersect the direction that the insulating gate portions extend and are parallel to each other.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, further comprising second well regions of the second conductivity type which are located at boundaries of the insulating gate portions and drift region and are connected to the first main electrode.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the drift region is made of silicon carbide, and the first main electrode includes a Schottky electrode which forms a Schottky junction with part of the drift region exposed in the major surface, and the unipolar diode is a Schottky barrier diode.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the drift region is made of silicon carbide,
the first main electrode includes a hetero electrode,
the hetero electrode is made of a semiconductor having a narrower energy band gap than that of the drift region, and
the unipolar diode is a heterojunction diode.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the unipolar diode operates with lower on-voltage than on-voltage of PN diodes formed between the drift region and the first well regions or between the first well regions and the source regions.