# US 8,786,009 B2 · Substrate structures including buried wiring, semiconductor devices including substrate structures, and method of fabricating the same

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- Number: US 8,786,009 B2
- Document ID: US8786009B2
- Status: Granted
- Kind: B2
- Application number: 12/902,247
- Filed: 2010-10-12
- Published: 2011-05-05
- Granted: 2014-07-22
- Earliest claimed: 2009-11-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Kang-Uk Kim; Yong-Chul Oh; Hui-Jung Kim; Hyun-Woo Chung; Hyun-Gi Kim
- Inventors: Kang-Uk Kim; Yong-Chul Oh; Hui-Jung Kim; Hyun-Woo Chung; Hyun-Gi Kim
- Web page: https://patentgrep.com/patent/US8786009B2

## CPC

- H10P 90/00: Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/482: {Bit lines}
- H10B 41/30: characterised by the memory core region
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/42: Simultaneous manufacture of periphery and memory cells
- H10P 10/12: {Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates (preparing SOI wafers using bonding H10P90/1914)}
- H10P 90/1904: {Preparing vertically inhomogeneous wafers}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/4432: {the principal metal being a noble metal, e.g. gold}
- H10W 20/4441: {the principal metal being a refractory metal}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate structure including a first substrate and a second substrate, and a buried wiring interposed between the first substrate and the second structure, where the buried wiring is in direct contact with the second substrate. The semiconductor device further includes a vertical transistor located in the second substrate of the substrate structure. The vertical transistor includes a gate electrode and a semiconductor pillar, and the buried wiring is one of source electrode or a drain electrode of the vertical transistor.

## Claims

### Claim 1

A substrate structure having a first region and a second region discrete from and disposed laterally of the first region and, comprising:
a first substrate and a second substrate juxtaposed with the first substrate in a vertical direction in both the first and second regions of the substrate structure;
buried wiring comprising an electrically conductive wiring layer,
wherein the buried wiring contacts the second substrate in the first region of the substrate structure, and the second region of the substrate structure is devoid of the buried wiring and includes a source/drain region; and
a contact plug extending through the second substrate from the source/drain region to the wiring layer of the buried wiring.

### Claim 2 (depends on 1)

The substrate structure of claim 1, wherein the buried wiring further comprises a barrier layer, and the barrier layer contacts the second substrate in the first region of the substrate structure.

### Claim 3 (depends on 2)

The substrate structure of claim 2, wherein the wiring layer is of at least one material selected from the group consisting of doped polysilicon, W, Ti, Ta, Mo, Ir, Hf, Zr, Ru, Pt, Ni, Al, WNx, AlNx, TaNx, TiNx, TiAlxNy, MoNx, HfNx, and ZrNx.

### Claim 4 (depends on 3)

The substrate structure of claim 3, wherein the barrier layer is at least one film of material selected from the group consisting of Ti, TiNx, TiSix, Ta, TaNx, TaSix, Mo, MoNx, Hf, HfNx, W, WNx, WSix, Zr, ZrNx, ZrSix, Ni, NiSix, Al, AlNx, and CoSix.

### Claim 5 (depends on 1)

The substrate structure of claim 1, wherein each of the second and first substrates independently consists of a silicon substrate, a germanium substrate, a silicon-germanium substrate, an SOI (Silicon-On-Insulator) substrate, and a GOI (Germanium-On-Insulator) substrate.

### Claim 6 (depends on 2)

The substrate structure of claim 2, further comprising an insulating layer interposed between the first substrate and the wiring layer.

### Claim 7 (depends on 1)

The substrate structure of claim 1, wherein the buried wiring is a bit line or a word line.

### Claim 8 (depends on 1)

The substrate structure of claim 1, wherein the buried wiring is an interconnection line.

### Claim 9 (depends on 1)

The substrate structure of claim 1, wherein the first and second substrates contact one another throughout the second region of the substrate structure.

### Claim 10 (depends on 9)

The substrate structure of claim 9, wherein the first region is a memory cell region, and the second region is a peripheral circuit region.

### Claim 11 (depends on 1)

The substrate structure of claim 1, further comprising an insulating layer, and wherein the buried wiring and the insulating layer are interposed between the second and first substrates in the first region of the substrate structure, and the insulating layer is interposed between the second and first substrates in the second region of the substrate structure.

### Claim 12 (depends on 11)

The substrate structure of claim 11, wherein the insulating layer includes a stack of two different insulating materials.

### Claim 13 (depends on 1)

The substrate structure of claim 1, further comprising an insulating layer and a compensation layer, and wherein the buried wiring and the insulating layer are interposed between the second and first substrates in the first region of the substrate structure, and the compensation layer is interposed between the second and first substrates in the second region of the substrate structure, and the combined thickness of the buried wiring and the first insulating layer is the same as the thickness of the compensation layer.

### Claim 14 (depends on 13)

The substrate structure of claim 13, wherein the compensation layer comprises at least one of an undoped polysilicon material and a semiconductor material.

### Claim 15 (depends on 1)

The substrate structure of claim 1, wherein the buried wiring consists of the electrically conductive wiring layer.

### Claim 16 (depends on 15)

The substrate structure of claim 15, wherein each of the second and first substrates independently consists of one of a silicon substrate, a germanium substrate, a silicon-germanium substrate, an SOI (Silicon-On-Insulator) substrate, and a GOI (Germanium-On-Insulator) substrate.

### Claim 17 (depends on 1)

The substrate structure of claim 1, wherein the buried wiring consists of the layer of electrically conductive wiring and a barrier layer of at least one film of material selected from the group consisting of Ti, TiNx, TiSix, Ta, TaNx, TaSix, Mo, MoNx, Hf, HfNx, W, WNx, WSix, Zr, ZrNx, ZrSix, Ni, NiSix, Al, AlNx, and CoSix, and the barrier layer contacts the second substrate.

### Claim 18 (depends on 17)

The substrate structure of claim 17, wherein each of the second and first substrates independently consists of one of a silicon substrate, a germanium substrate, a silicon-germanium substrate, an SOI (Silicon-On-Insulator) substrate, and a GOI (Germanium-On-Insulator) substrate.

### Claim 19 (depends on 1)

The substrate structure of claim 1, wherein the electrically conductive wiring layer consists of a layer of conductive material extending substantially parallel to the first and second substrates in the first region.