# US 8,786,008 B2 · Nonvolatile semiconductor memory device and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,008 B2 - Document ID: US8786008B2 - Status: Granted - Kind: B2 - Application number: 13/420,745 - Filed: 2012-03-15 - Published: 2013-03-07 - Granted: 2014-07-22 - Earliest claimed: 2011-09-02 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Megumi Ishiduki; Masaru Kidoh; Mitsuru Sato; Masaru Kito; Ryota Katsumata - Inventors: Megumi Ishiduki; Masaru Kidoh; Mitsuru Sato; Masaru Kito; Ryota Katsumata - Web page: https://patentgrep.com/patent/US8786008B2 ## CPC - H10D 30/693: {Vertical IGFETs having charge trapping gate insulators} - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate} - H10D 64/037: {comprising charge-trapping insulators} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body; a memory film; a first channel body layer provided inside the memory film; an interlayer insulating film provided on the first stacked body; a second stacked body having a select gate electrode layer, and a second insulating layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating film in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole. A first pore diameter of the second hole at an upper end of the select gate electrode layer is smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer. ## Claims ### Claim 1 A nonvolatile semiconductor memory device, comprising: a first stacked body having a plurality of electrode layers and a plurality of first insulating layers which are stacked alternately; a memory film provided on a side wall of a first hole penetrating the first stacked body in a stacking direction of the first stacked body; a first channel body layer provided inside the memory film provided in the first hole; an interlayer insulating film provided on the first stacked body; a second stacked body having a select gate electrode layer provided on the interlayer insulating film, and a second insulating layer provided on the select gate electrode layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating film in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole, and connected to the first channel body layer, a first pore diameter of the second hole at an upper end of the select gate electrode layer being smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer. ### Claim 2 (depends on 1) The device according to claim 1, wherein a pore diameter of the second hole becomes gradually larger from the upper end toward the lower end of the select gate electrode layer. ### Claim 3 (depends on 1) The device according to claim 1, wherein a third pore diameter of the second hole between the upper end and the lower end is larger than the first pore diameter. ### Claim 4 (depends on 3) The device according to claim 3, wherein the third pore diameter is larger than the second pore diameter. ### Claim 5 (depends on 1) The device according to claim 1, wherein a third pore diameter of the second hole at a position between the upper end and the lower end is larger than the first pore diameter, and a pore diameter of the second hole from a position of the third pore diameter to the lower end is substantially constant. ### Claim 6 (depends on 1) The device according to claim 1, wherein a difference between the first pore diameter and the second pore is 5 nanometers or more. ### Claim 7 (depends on 1) The device according to claim 1, wherein a part of the second channel body layer includes impurity, the part is provided inside the second hole which penetrates the second insulating layer. ### Claim 8 (depends on 1) The device according to claim 1, wherein a part of the second channel body layer includes impurity whose concentration is not less than 5×1019 atoms/cm3, the part is provided inside the second hole which penetrates the second insulating layer. ### Claim 9 (depends on 1) The device according to claim 1, wherein a fourth pore diameter of the second hole at a lower end of the second insulating layer is larger than the first pore diameter. ### Claim 10 (depends on 9) The device according to claim 9, wherein a difference between the first pore diameter and the fourth pore is 10 nanometers or more. ### Claim 11 A nonvolatile semiconductor memory device, comprising: a first stacked body having a plurality of electrode layers and a plurality of first insulating layers which are stacked alternately; a memory film provided on a side wall of a first hole penetrating the first stacked body in a stacking direction of the first stacked body; a first channel body layer provided inside the memory film provided in the first hole; an interlayer insulating film provided on the first stacked body; a second stacked body having a select gate electrode layer provided on the interlayer insulating film, and a second insulating layer provided on the select gate electrode layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating film in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole, and connected to the first channel body layer, a first pore diameter of the second hole of the select gate electrode layer side in a first interface between the select gate electrode layer and the second insulating layer being smaller than a second pore diameter of the second hole of the select gate electrode layer side in a second interface between the select gate electrode layer and the interlayer insulating film. ### Claim 12 (depends on 11) The device according to claim 11, wherein a pore diameter of the second hole becomes gradually larger from the first interface toward the second interface. ### Claim 13 (depends on 11) The device according to claim 11, wherein a third pore diameter of the second hole between the first interface and the second interface is larger than the first pore diameter. ### Claim 14 (depends on 13) The device according to claim 13, wherein the third pore diameter is larger than the second pore diameter. ### Claim 15 (depends on 11) The device according to claim 11, wherein a third pore diameter of the second hole at a position between the first interface and the second interface is larger than the first pore diameter, and a pore diameter of the second hole from a position of the third pore diameter to the second interface is substantially constant. ### Claim 16 (depends on 11) The device according to claim 11, wherein a difference between the first pore diameter and the second pore diameter is 5 nanometers or more. ### Claim 17 (depends on 11) The device according to claim 11, wherein a fourth pore diameter of the second hole of the second insulating layer side in the first interface is larger than the first pore diameter.