# US 8,786,007 B2 · Three-dimensional nonvolatile memory device

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- Number: US 8,786,007 B2
- Document ID: US8786007B2
- Status: Granted
- Kind: B2
- Application number: 12/592,871
- Filed: 2009-12-03
- Published: 2010-06-03
- Granted: 2014-07-22
- Earliest claimed: 2008-12-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Soodoo Chae; Myoungbum Lee
- Inventors: Soodoo Chae; Myoungbum Lee
- Web page: https://patentgrep.com/patent/US8786007B2

## CPC

- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, and a plurality of gate electrodes. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicular to the semiconductor substrate. The gate electrodes include a first gate electrode and a second gate electrode. The first gate electrode is disposed on the memory cell region to intersect the active pillars. The second gate electrode is disposed on the contact region, connected to the first gate electrode and comprising metal material.

## Claims

### Claim 1

A nonvolatile memory device comprising:
a semiconductor substrate including a memory cell region and a contact region;
a plurality of gate electrodes substantially parallel to an upper surface of the semiconductor substrate, each of the gate electrodes including a first gate electrode disposed on the memory cell region and a second gate electrode disposed on the contact region, connected to an end portion of the first gate electrode; and
a plurality of active pillars extending in the memory cell region perpendicular to the semiconductor substrate,
wherein the first and the second gate electrodes are comprised of different conductive materials from each other.

### Claim 2 (depends on 1)

The nonvolatile memory device of claim 1, wherein
the gate electrodes are stacked on the semiconductor substrate, with an interlayer dielectric there between; and
an edge portion of the second gate electrode included in a lower gate electrode among the gate electrodes is exposed by the second gate electrode included in an upper gate electrode which is disposed on the lower gate electrode.

### Claim 3 (depends on 1)

The nonvolatile memory device of claim 1, further comprising contact plugs connected respectively to the second gate electrodes of the contact region.

### Claim 4 (depends on 1)

The nonvolatile memory device of claim 1, further comprising a plurality of supporters extending in the contact region perpendicular to the semiconductor substrate to penetrate the gate electrodes.

### Claim 5 (depends on 4)

The nonvolatile memory device of claim 4, wherein an interface surface between the first gate electrode and the second gate electrode is disposed between the active pillar and the supporter.

### Claim 6 (depends on 1)

The nonvolatile memory device of claim 1, wherein the first gate electrode of the memory cell region is comprised of polysilicon and the second gate electrode of the contact region is comprised of metal material.

### Claim 7 (depends on 1)

The nonvolatile memory device of claim 1, further comprising a data storage layer between the active pillars and the gate electrodes.

### Claim 8 (depends on 1)

The nonvolatile memory device of claim 1, wherein
the gate electrodes are stacked on the semiconductor substrate, with an interlayer dielectric there between; and
the areas of the gate electrodes decrease with an increase in the distance from the semiconductor substrate.

### Claim 9 (depends on 1)

The nonvolatile memory device of claim 1, wherein the contact region is disposed around the memory cell region.

### Claim 10 (depends on 1)

The nonvolatile memory device of claim 1, wherein the contact region is disposed at both side portions of the memory cell region.