# US 8,786,006 B2 · Flash memory device having a graded composition, high dielectric constant gate insulator

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- Number: US 8,786,006 B2
- Document ID: US8786006B2
- Status: Granted
- Kind: B2
- Application number: 13/595,219
- Filed: 2012-08-27
- Published: 2012-12-13
- Granted: 2014-07-22
- Earliest claimed: 2005-04-26
- Assignees: Micron Technology, Inc.
- Applicants: Leonard Forbes; Kie Y. Ahn
- Inventors: Leonard Forbes; Kie Y. Ahn
- Web page: https://patentgrep.com/patent/US8786006B2

## CPC

- H10B 41/00: Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B 99/22: {including field-effect components}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10B 43/00: EEPROM devices comprising charge-trapping gate insulators
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator comprises amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate.

## Claims

### Claim 1

A memory cell, comprising:
a semiconductor;
a charge storage structure;
a control gate;
amorphous silicon carbide between the semiconductor and the charge storage structure; and
a graded composition insulator material between the charge storage structure and the control gate.

### Claim 2 (depends on 1)

The memory cell of claim 1, wherein the graded composition insulator material comprises pairs of high-permittivity insulating materials taken from a list of materials, the list of materials comprising: Si3N4, Al2O3, Y2O3, La2O3, Ta2O5, TiO2, HfO2, ZrO2, SiC and GeXCY.

### Claim 3 (depends on 1)

The memory cell of claim 1, wherein the memory cell is a vertical memory cell.

### Claim 4 (depends on 1)

The memory cell of claim 1, and further including forming a silicon oxide between the semiconductor and the amorphous silicon carbide.

### Claim 5 (depends on 2)

The memory cell of claim 2, wherein the high permittivity insulating materials have a dielectric constant greater than 3.9.

### Claim 6 (depends on 1)

The memory cell of claim 1, wherein the semiconductor comprises germanium.

### Claim 7 (depends on 1)

The memory cell of claim 1, wherein a barrier of the graded composition material is reduced responsive to a composition ratio of the graded composition material.

### Claim 8 (depends on 1)

The memory cell of claim 1, further including the amorphous silicon carbide being part of a tunnel insulator that is graded from silicon oxide nearest the semiconductor to silicon carbide to germanium carbide nearest the charge storage structure.

### Claim 9 (depends on 1)

The memory cell of claim 1, further including silicon oxide between the amorphous silicon carbide and the semiconductor.

### Claim 10 (depends on 1)

The memory cell of claim 1, wherein the memory cell is part of a NAND non-volatile memory array.

### Claim 11

A memory cell, comprising:
a semiconductor substrate;
a floating gate charge storage structure;
a control gate;
amorphous silicon carbide between the semiconductor substrate and the charge storage structure; and
a graded composition insulator material between the charge storage structure and the control gate.

### Claim 12 (depends on 11)

The memory cell of claim 11, wherein the graded composition insulator material comprises a silicon carbide material graded to a germanium carbide material.

### Claim 13 (depends on 11)

The memory cell of claim 11, wherein each material of the graded composition insulator material comprises a dielectric material having a dielectric constant greater than SiO2.

### Claim 14 (depends on 11)

The memory cell of claim 11, further comprising doped regions formed in the semiconductor substrate, and where the semiconductor substrate comprises a silicon semiconductor substrate.

### Claim 15 (depends on 14)

The memory cell of claim 14, wherein the doped regions comprise n+ regions and where the semiconductor substrate comprises a p+ type substrate.

### Claim 16 (depends on 14)

The memory cell of claim 14, wherein the doped regions comprise p+ regions and where the semi substrate comprises an n+ type substrate.

### Claim 17 (depends on 11)

The memory cell of claim 11, wherein the floating gate and the control gate comprise polysilicon.

### Claim 18 (depends on 11)

The memory cell of claim 11, further including the amorphous silicon carbide being part of a tunnel insulator that is graded from silicon oxide nearest the semiconductor to silicon carbide to germanium carbide nearest the charge storage structure.

### Claim 19

A memory cell, comprising:
a semiconductor substrate;
a floating gate charge storage structure;
a control gate;
a tunnel insulator comprising amorphous silicon carbide and germanium carbide between the semiconductor substrate and the charge storage structure; and
a graded composition insulator material between the charge storage structure and the control gate.

### Claim 20 (depends on 19)

The memory cell of claim 19, wherein the graded composition insulator material comprises a graded composition of silicon carbide and germanium carbide.

### Claim 21 (depends on 19)

The memory cell of claim 19, wherein the tunnel insulator comprising amorphous silicon carbide and germanium carbide comprises a graded composition of amorphous silicon carbide and germanium carbide.