# US 8,786,002 B2 · Semiconductor device

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- Number: US 8,786,002 B2
- Document ID: US8786002B2
- Status: Granted
- Kind: B2
- Application number: 13/151,306
- Filed: 2011-06-02
- Published: 2011-12-29
- Granted: 2014-07-22
- Earliest claimed: 2010-06-29
- Assignees: Renesas Electronics Corporation
- Applicants: Masao Kondo; Masatoshi Morikawa; Satoshi Goto
- Inventors: Masao Kondo; Masatoshi Morikawa; Satoshi Goto
- Web page: https://patentgrep.com/patent/US8786002B2

## CPC

- H10D 1/64: Variable-capacitance diodes, e.g. varactors
- H04B 1/48: in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter {(H04B1/46 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H04B: TRANSMISSION

## Abstract

In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level.

## Claims

### Claim 1

A semiconductor device, comprising:
an antenna switch having a transmission terminal, an antenna terminal, and a reception terminal,
wherein the antenna switch is a semiconductor device having:
(a) a plurality of first field effect transistors coupled in series between the transmission terminal and the antenna terminal; and
(b) a plurality of second field effect transistors coupled in series between the reception terminal and the antenna terminal, and
wherein, between a source region and a drain region of each of the second field effect transistors coupled in series, a capacitance circuit is coupled which has a voltage dependency such that, in either of cases where a positive voltage is applied to the drain region based on a potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, a capacitance decreases to a value smaller than that in a state where the potential of the source region and a potential of the drain region are at the same level,
wherein the capacitance circuit comprises a first MOS diode capacitance element and a second MOS diode capacitance element which are formed over a SOI substrate including a support substrate, a buried insulating layer formed over the support substrate, and a semiconductor layer formed over the buried insulating layer,
wherein the first MOS diode capacitance element has:
(c1) a first semiconductor region of a first conductivity type formed in the semiconductor layer;
(c2) a first capacitance insulating film formed over the first semiconductor region; and
(c3) a first electrode formed over the first capacitance insulating film,
wherein the second MOS diode capacitance element has:
(d1) a second semiconductor region of the first conductivity type formed in the semiconductor layer;
(d2) a second capacitance insulating film formed over the second semiconductor region; and
(d3) a second electrode formed over the second capacitance insulating film, and
wherein the capacitance circuit includes a first terminal electrically coupled to the first semiconductor region of the first MOS diode capacitance element, and a second terminal electrically coupled to the second semiconductor region of the second MOS diode capacitance element, and has a configuration in which the first electrode of the first MOS diode capacitance element is electrically coupled to the second electrode of the second MOS diode capacitance element.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the capacitance circuit further has a first resistance element provided between the first terminal and the first electrode, and a second resistance element provided between the second terminal and the second electrode, and
wherein a resistance value of the first resistance element is the same as a resistance value of the second resistance element.