# US 8,785,998 B2 · Semiconductor device having vertical channel transistor and methods of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,998 B2 - Document ID: US8785998B2 - Status: Granted - Kind: B2 - Application number: 13/724,799 - Filed: 2012-12-21 - Published: 2013-05-09 - Granted: 2014-07-22 - Earliest claimed: 2010-05-20 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hyung-woo Chung; Yong-chul Oh; Yoo-sang Hwang; Gyo-young Jin; Hyeong-sun Hong; Dae-ik Kim - Web page: https://patentgrep.com/patent/US8785998B2 ## CPC - H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells} - H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)} - H10B 12/482: {Bit lines} - H10D 89/10: Integrated device layouts - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor memory device includes a first pair of pillars extending from a substrate to form vertical channel regions, the first pair of pillars having a first pillar and a second pillar adjacent to each other, the first pillar and the second pillar arranged in a first direction, a first bit line disposed on a bottom surface of a first trench formed between the first pair of pillars, the first bit line extending in a second direction that is substantially perpendicular to the first direction, a first contact gate disposed on a first surface of the first pillar with a first gate insulating layer therebetween, a second contact gate disposed on a first surface of the second pillar with a second gate insulating layer therebetween, the first surface of the first pillar and the first surface of the second pillar face opposite directions, and a first word line disposed on the first contact gate and a second word line disposed on the second contact gate, the word lines extending in the first direction. ## Claims ### Claim 1 A semiconductor memory device comprising: a plurality of pillars extending from a substrate to form vertical channel regions; a word line disposed between two adjacent rows of the pillars; a bit line disposed between two adjacent columns of the pillars, the bit line in contact with a bottom surface of a first trench formed between a first pair of pillars positioned in a row direction, the first pair of pillars having a first pillar and a second pillar; and a contact gate disposed between a second pair of pillars positioned in a column direction, the second pair of pillars having the second pillar and a third pillar, the contact gate comprising a first surface and a second surface, the first surface in contact with the word line, the second surface in contact with a gate insulating layer disposed on the second pillar. ### Claim 2 (depends on 1) The device of claim 1, wherein a distance from an upper surface of the substrate to a bottom surface of the contact gate is less than a distance from the upper surface of the substrate to an upper surface of the bit line. ### Claim 3 (depends on 1) The device of claim 1, wherein the first pair of pillars and the substrate comprise a semiconductor material. ### Claim 4 (depends on 1) The device of claim 1, further comprising a nitride liner, a sidewall oxide layer, and a gap fill oxide layer respectively stacked on a sidewall of the first trench. ### Claim 5 (depends on 1) The device of claim 1, further comprising a first source/drain region formed around the bottom surface of the first trench. ### Claim 6 (depends on 5) The device of claim 5, wherein each end portion of the first pair of pillars comprises a second source/drain region. ### Claim 7 (depends on 1) The device of claim 1, further comprising a first contact plug and a second contact plug respectively disposed on each end portion of the first pillar and the second pillar. ### Claim 8 (depends on 7) The device of claim 7, wherein a lower electrode of a capacitor is disposed on the first contact plug. ### Claim 9 (depends on 7) The device of claim 7, further comprising a spacer disposed between the first contact plug and the first contact gate. ### Claim 10 (depends on 9) The device of claim 9, wherein the spacer has a ring shape. ### Claim 11 (depends on 6) The device of claim 6, wherein a channel region is formed between the first source/drain region and the second source/drain region. ### Claim 12 (depends on 1) The device of claim 1, wherein the bit line comprises a first portion disposed between the first pair of pillars and a second portion disposed between a third pair of pillars neighboring immediately next to the first pair of pillars in the column direction, the first portion in contact with the bottom surface of the first trench comprising a semiconductor material, the second portion in contact with the bottom surface of a second trench comprising an insulating material. ### Claim 13 (depends on 12) The device of claim 12, the first portion and the second portion has a same width. ### Claim 14 (depends on 12) The device of claim 12, wherein the first portion and the second portion has a same thickness. ### Claim 15 (depends on 12) The device of claim 12, wherein an upper surface of the first portion is coplanar with an upper surface of the second portion. ### Claim 16 (depends on 12) The device of claim 12, wherein the first portion has a smaller thickness than the second portion. ### Claim 17 (depends on 12) The device of claim 12, wherein a top width of the second portion is wider than a bottom width of the second portion. ### Claim 18 (depends on 12) The device of claim 12, wherein a lower portion of the second portion is narrower than a lower portion of the first portion. ### Claim 19 (depends on 12) The device of claim 12, wherein a curvature of a lower end of the second portion is greater than a curvature of a lower end of the first portion. ### Claim 20 (depends on 12) The device of claim 12, wherein a width of the first portion is smaller than a width of the second portion. ### Claim 21 (depends on 1) The device of claim 1, wherein each of the pillars has a same width. ### Claim 22 (depends on 1) The device of claim 1, wherein the bit line comprises at least one of W, Al, Cu, Mo, Ti, Ta, Ru, TiN, TiN/W, Ti/TiN, WN, W/WN, TaN, Ta/TaN, TiSiN, TaSiN, WSiN, CoSi2, TiSi2, or WSi2.