# US 8,785,997 B2 · Semiconductor device including a silicate glass structure and method of manufacturing a semiconductor device

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- Number: US 8,785,997 B2
- Document ID: US8785997B2
- Status: Granted
- Kind: B2
- Application number: 13/473,231
- Filed: 2012-05-16
- Published: 2013-11-21
- Granted: 2014-07-22
- Earliest claimed: 2012-05-16
- Assignees: Infineon Technologies AG
- Applicants: Hans-Joachim Schulze; Alexander Susiti; Markus Zundel; Reinhard Ploss
- Inventors: Hans-Joachim Schulze; Alexander Susiti; Markus Zundel; Reinhard Ploss
- Web page: https://patentgrep.com/patent/US8785997B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/663: {having both source contacts and drain contacts on the same surface, i.e. up-drain VDMOS}
- H10D 30/665: {having edge termination structures}
- H10D 62/10: Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10P 14/40: of conductive or resistive materials
- H10P 14/6518: {by introduction of substances into an already-existing insulating layer}
- H10P 14/6903: {containing silicon}
- H10P 14/6923: {the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/40: into insulating materials
- H10P 32/20: Diffusion for doping of insulating layers
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor body including a first surface. The semiconductor device further includes a continuous silicate glass structure over the first surface. A first part of the continuous glass structure over an active area of the semiconductor body includes a first composition of dopants that differs from a second composition of dopants in a second part of the continuous glass structure over an area of the semiconductor body outside of the active area.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor body including a first surface;
a continuous silicate glass structure over the first surface; and wherein
a first part of the continuous glass structure over an active area of the semiconductor body includes a first composition of dopants that differs from a second composition of dopants in a second part of the continuous glass structure over an edge termination area of the semiconductor body outside of the active area; and wherein the active area comprises a source that is absent in the edge termination area.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a gate electrode is arranged in the active area and the gate electrode is absent in the area outside of the active area.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein at least one wiring level including a metal is arranged over the continuous silicate glass structure and a wiring level including a metal is absent between the continuous silicate glass structure and the first surface of the semiconductor body.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first part of the continuous glass structure includes a borophosphosilicate glass layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the first part of the continuous glass structure includes a layer stack and the borophosphosilicate glass layer is a lowermost layer of the layer stack and has a shorter distance to the first surface of the semiconductor body than an uppermost layer of the layer stack.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the layer stack includes at least one of a borosilicate glass layer and a phosphosilicate glass layer over the borophosphosilicate glass layer.

### Claim 7 (depends on 1)

The semiconductor layer of claim 1, wherein the first part of the continuous glass structure includes at least one borosilicate/phosphosilicate or phosphosilicate/borosilicate glass layer as a lowermost layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the second part includes a phosphosilicate glass layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the second part includes a borophosphosilicate glass layer on the phosphosilicate glass layer or the phosphosilicate glass layer on a borophosphosilicate glass layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the second part is a double layer.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the second part includes at least two layers of a phosphosilicate glass layer, a borosilicate glass layer and a borophosphosilicate glass layer, and wherein the second part further includes an undoped silicate glass layer on top and/or at a bottom of the at least two layers.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the first part of the continuous glass structure includes a lowermost borophosphosilicate glass layer and a layer structure on the borophosphosilicate glass layer, and wherein the second part of the continuous glass structure consists of the layer structure.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein a medium thickness of the first part of the continuous silicate glass structure differs from a medium thickness of the second part of the continuous silicate glass structure.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the second part of the continuous glass structure includes a concentration of at least one of phosphor and boron that decreases by at least a factor of two between a first side and a second side of the second part of the continuous glass structure, wherein the second side is closer to the first surface of the semiconductor body than the first side.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein an implantation dose of the at least one of phosphor and boron is in a range between 5×1016 cm−2 and 5×1017 cm−2.