# US 8,785,995 B2 · Ferroelectric semiconductor transistor devices having gate modulated conductive layer

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- Number: US 8,785,995 B2
- Document ID: US8785995B2
- Status: Granted
- Kind: B2
- Application number: 13/108,340
- Filed: 2011-05-16
- Published: 2012-11-22
- Granted: 2014-07-22
- Earliest claimed: 2011-05-16
- Assignees: International Business Machines Corporation
- Applicants: Catherine A. Dubourdieu; David J. Frank; Martin M. Frank; Vijay Narayanan; Paul M. Solomon; Thomas N. Theis
- Inventors: Catherine A. Dubourdieu; David J. Frank; Martin M. Frank; Vijay Narayanan; Paul M. Solomon; Thomas N. Theis
- Web page: https://patentgrep.com/patent/US8785995B2

## CPC

- H10D 64/511: {for IGFETs}
- H10D 30/87: FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] {(FETs having Schottky contact on top of heterojunction gate H10D30/801)}
- H10D 64/411: {for FETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Ferroelectric semiconductor switching devices are provided, including field effect transistor (FET) devices having gate stack structures formed with a ferroelectric layer disposed between a gate contact and a thin conductive layer (“quantum conductive layer”). The gate contact and ferroelectric layer serve to modulate an effective work function of the thin conductive layer. The thin conductive layer with the modulated work function is coupled to a semiconductor channel layer to modulate current flow through the semiconductor and achieve a steep sub-threshold slope.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a first source/drain contact and a second source/drain contact formed on the semiconductor substrate; and
a gate structure formed on the semiconductor substrate between the first and second source/drain contacts, wherein the gate structure comprises:
a conductive layer disposed over the semiconductor substrate;
a ferroelectric layer disposed over the conductive layer; and
a gate contact layer disposed over the ferroelectric layer;
wherein the conductive layer of the gate structure is electrically connected to the first source/drain contact, and wherein the conductive layer is a non-semiconductor layer in direct contact with the first source/drain contact.

### Claim 2 (depends on 1)

The device of claim 1, wherein the gate structure further comprises an insulating layer between the conductive layer and the semiconductor substrate.

### Claim 3 (depends on 1)

The device of claim 1, wherein the conductive layer comprises a carbon nanostructure.

### Claim 4 (depends on 3)

The device of claim 3, wherein the carbon nanostructure comprises one or more carbon nanotubes.

### Claim 5 (depends on 1)

The device of claim 1, wherein the conductive layer comprises doped STO (Strontium Titanate).

### Claim 6 (depends on 1)

The device of claim 1, wherein the conductive layer comprises TaN or TaSiN.

### Claim 7 (depends on 1)

The device of claim 1, wherein the conductive layer comprises a transparent conducting oxide material.

### Claim 8 (depends on 1)

The device of claim 1, wherein the conductive layer has a thickness of 3 nanometers or less.

### Claim 9 (depends on 1)

The device of claim 1, wherein the conductive layer has a carrier density of 1×1021 charges per cubic centimeter.

### Claim 10 (depends on 1)

The device of claim 1, wherein the semiconductor substrate comprises an insulating region, wherein the first source/drain contact is formed on the insulating region of the semiconductor substrate.

### Claim 11

A semiconductor device, comprising:
a semiconductor substrate;
a first source/drain contact and a second source/drain contact formed on the semiconductor substrate;
a control voltage contact;
a gate structure formed on the semiconductor substrate, wherein the gate structure comprises:
a conductive layer disposed over the semiconductor substrate;
a ferroelectric layer disposed over the conductive layer; and
a gate contact layer disposed over the ferroelectric layer; and
wherein the conductive layer of the gate structure is electrically connected to the control voltage contact, and wherein the conductive layer is a non-semiconductor layer in direct contact with the control voltage contact.

### Claim 12

A semiconductor device, comprising:
a semiconductor substrate;
a conductive layer formed directly on, and in contact with, the semiconductor substrate, the conductive layer formed of a non-semiconductor material having a thickness of three nanometers or less; and
a ferroelectric layer disposed over the conductive layer, wherein the ferroelectric layer has an effective negative capacitance that counteracts a capacitance provided by the conductive layer;
wherein the ferroelectric layer and the conductive layer form a gate structure of an FET device,
a contact layer disposed over the ferroelectric layer; and
a first source/drain contact and a second source/drain contact disposed on opposing sides of the gate structure, wherein the conductive layer is in direct contact with the first source/drain contact.

### Claim 13 (depends on 12)

The device of claim 12, wherein the conductive layer effectively modulates current flow in the semiconductor substrate to provide a sub-threshold slope of about 50 mV/decade or less.

### Claim 14 (depends on 12)

The device of claim 12, wherein the semiconductor substrate comprises an insulating layer, wherein the first source/drain contact is formed on the insulating layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further comprising a doped region formed in the semiconductor substrate below the gate structure, wherein the conductive layer is in contact with the doped region.

### Claim 16

A semiconductor integrated circuit, comprising a semiconductor substrate, and a plurality of semiconductor devices formed on the semiconductor substrate, each of the plurality of semiconductor devices comprising:
a first source/drain contact and a second source/drain contact formed on the semiconductor substrate; and
a gate structure formed on the semiconductor substrate between the first and second source/drain contacts, wherein the gate structure comprises:
a conductive layer disposed over the semiconductor substrate;
a ferroelectric layer disposed over the conductive layer; and
a gate contact layer disposed over the ferroelectric layer;
wherein the conductive layer of the gate structure is electrically connected to the first source/drain contact, and wherein the conductive layer is a non-semiconductor layer in direct contact with the first source/drain contact.

### Claim 17 (depends on 16)

The semiconductor integrated circuit of claim 16, wherein the gate structure further comprises an insulating layer between the conductive layer and the semiconductor substrate.

### Claim 18 (depends on 16)

The semiconductor integrated circuit of claim 16, wherein the conductive layer comprises a carbon nanostructure.

### Claim 19 (depends on 16)

The semiconductor integrated circuit of claim 16, wherein the conductive layer comprises doped STO (Strontium Titanate).

### Claim 20 (depends on 16)

The semiconductor integrated circuit of claim 16, wherein the conductive layer comprises TaN or TaSiN.

### Claim 21 (depends on 16)

The semiconductor integrated circuit of claim 16, wherein the conductive layer comprises a transparent conducting oxide material.

### Claim 22 (depends on 16)

The semiconductor integrated circuit of claim 16, wherein the conductive layer has a thickness of 3 nanometers or less.

### Claim 23 (depends on 16)

The semiconductor integrated circuit of claim 16, wherein the conductive layer has a carrier density of 1×1021 charges per cubic centimeter.