# US 8,785,989 B2 · Semiconductor constructions

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- Number: US 8,785,989 B2
- Document ID: US8785989B2
- Status: Granted
- Kind: B2
- Application number: 13/108,847
- Filed: 2011-05-16
- Published: 2011-09-08
- Granted: 2014-07-22
- Earliest claimed: 2006-01-27
- Assignees: Micron Technology, Inc.
- Applicants: Lucien J. Bissey; William A. Stanton
- Inventors: Lucien J. Bissey; William A. Stanton
- Web page: https://patentgrep.com/patent/US8785989B2

## CPC

- G03F 7/0035: {Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the topography having two or more surfaces of differing reflectivity relative to one another. The invention also includes methods of patterning photoresist in which a saturable absorption layer is provided between the photoresist and a topography with surfaces of differing reflectivity, and in which the differences in reflectivity are utilized to enhance the accuracy with which an image is photolithographically formed in the photoresist.

## Claims

### Claim 1

A semiconductor construction, comprising:
a semiconductor substrate;
in at least one cross-sectional view, spaced projections over the substrate, the spaced projections being spaced from one another by an intervening region;
a first layer over the spaced projections and over the intervening region between the spaced projections, at least one of the following two uppermost surfaces terminating at a bottommost surface of the first layer: an uppermost surface of respective space projections and an uppermost surface of an intervening region;
an optically saturable absorption layer over the first layer;
photoresist over the optically saturable absorption layer; and
wherein the spaced projections correspond to an upwardly-opening container structure, and wherein the intervening region comprises insulative material within the container structure.

### Claim 2 (depends on 1)

The construction of claim 1 wherein the spaced projections comprise conductively-doped silicon capped with metal silicide.

### Claim 3 (depends on 1)

The construction of claim 1 wherein the spaced projections correspond to pedestals, and wherein the intervening region comprises a transistor gate stack.

### Claim 4 (depends on 1)

The construction of claim 1 wherein the optically saturable absorption layer comprises a plurality of optically saturable absorption layers.

### Claim 5 (depends on 1)

The construction of claim 1 further comprising a source/drain for a transistor, the source/drain in contact with one of the spaced projections.

### Claim 6 (depends on 1)

The construction of claim 1 further comprising a capacitor storage node in contact with at least one of the following: the spaced projections, the first layer and material in the intervening region.

### Claim 7

A semiconductor construction, comprising:
a semiconductor substrate;
in at least one cross-sectional view, spaced projections over the substrate, the spaced projections being spaced from one another by an intervening region;
a first layer over the spaced projections and over the intervening region between the spaced projections;
an optically saturable absorption layer over the first layer;
photoresist over the optically saturable absorption layer;
a capacitor storage node in contact with one of the spaced projections; and
wherein the capacitor storage node is located only in material in the intervening region.

### Claim 8 (depends on 7)

The construction of claim 7 wherein the capacitor storage node is further in contact with at least one of the following: the first layer and material in the intervening region.

### Claim 9 (depends on 8)

The construction of claim 8 wherein the capacitor storage node is further in contact with both of the first layer and the material in the intervening region.

### Claim 10

A semiconductor construction, comprising:
a semiconductor substrate;
in at least one cross-sectional view, spaced projections over the substrate, the spaced projections being spaced from one another by an intervening region;
a first layer over the spaced projections and over the intervening region between the spaced projections;
an optically saturable absorption layer over the first layer;
photoresist over the optically saturable absorption layer; and
an opening for a capacitor storage node, the opening extends through at least two of the following: material in the intervening region, the first layer, the optically saturable absorption layer and the photoresist.

### Claim 11 (depends on 10)

The construction of claim 10 further comprising capacitor storage node material in only the material of the intervening region.

### Claim 12 (depends on 10)

The construction of claim 10 wherein the opening extends into at least three of the following: the material of the intervening region, the first layer, the optically saturable absorption layer and the photoresist.

### Claim 13 (depends on 10)

The construction of claim 10 further comprising capacitor storage node material in contact with one of the spaced projections and wherein the opening is over the capacitor storage node material.