# US 8,785,988 B1 · N-channel metal-oxide field effect transistor with embedded high voltage junction gate field-effect transistor

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- Number: US 8,785,988 B1
- Document ID: US8785988B1
- Status: Granted
- Kind: B1
- Application number: 13/740,006
- Filed: 2013-01-11
- Published: 2014-07-17
- Granted: 2014-07-22
- Earliest claimed: 2013-01-11
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Wing-Chor Chan; Li-Fan Chen; Chen-Yuan Lin
- Web page: https://patentgrep.com/patent/US8785988B1

## CPC

- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 84/40: characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D 84/82: of only field-effect components
- H10D 30/83: FETs having PN junction gate electrodes
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device comprising a high-voltage (HV) n-type metal oxide semiconductor (NMOS) embedded HV junction gate field-effect transistor (JFET) is provided. An HV NMOS with embedded HV JFET may include, according to a first example embodiment, a substrate, an N-type well region disposed adjacent to the substrate, a P-type well region disposed adjacent to the N-type well region, and first and second N+ doped regions disposed adjacent to the N-type well and on opposing sides of the P-type well region. The P-type well region may comprise a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.

## Claims

### Claim 1

A semiconductor device comprising:
a P-type substrate; an N-type well region disposed adjacent to the substrate;
a P-type well region disposed adjacent to the N-type well region; and
first and second N+ doped regions disposed adjacent to the N-type well region and on opposing sides of the P-type well region;
wherein the P-type well region comprises a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the P-type well region is a first P-type well region, and further comprising a second P-type well region, the N-type well region encompassing the first and second P-type well regions such that at least a portion of the N-type well region is interposed between the first and second P-type well regions.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising first, second, and third field oxide (FOX) portions disposed adjacent to the N-type well region, the first FOX portion being further disposed adjacent to the first N+ doped region, the second FOX portion being further interposed between the first N+ doped region and the P+ doped portion, and the third FOX portion being interposed between the P-type well region and the second N+ doped region and further interposed between the gate structure and the P-type well region.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising an N-type layer and a P-top layer disposed adjacent to the N-type well region, the N-type layer being interposed between the third FOX portion and the P-top portion.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, further comprising an additional P-type well region disposed adjacent to the N-type well region and interposed between the first FOX portion and the P-type substrate.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a source of a junction gate field-effect transistor (JFET) is associated with the first N+ doped region, a drain of the JFET is associated with the second N+ doped region, and a gate of the JFET is associated with the P+ doped region and the third N+ doped region.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein a source of an n-channel metal-oxide field effect transistor (NMOS) is associated with the P+ doped region and the third N+ doped region, and a drain of the NMOS is associated with the second N+ doped region.

### Claim 8

A method for manufacturing a semiconductor device comprising:
providing a P-type substrate;
providing an N-type well region disposed adjacent to the substrate;
providing a P-type well region disposed adjacent to the N-type well region; and
providing first and second N+ doped regions disposed adjacent to the N-type well region and on opposing sides of the P-type well region;
wherein the P-type well region comprises a P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure.

### Claim 9 (depends on 8)

The method of claim 8, wherein providing the P-type well region comprises providing a first P-type well region, and further comprising providing a second P-type well region, the N-type well region encompassing the first and second P-type well regions such that at least a portion of the N-type well region is interposed between the first and second P-type well regions.

### Claim 10 (depends on 8)

The method of claim 8, further comprising providing first, second, and third field oxide (FOX) portions disposed adjacent to the N-type well region, the first FOX portion being further disposed adjacent to the first N+ doped region, the second FOX portion being further interposed between the first N+ doped region and the P+ doped portion, and the third FOX portion being interposed between the P-type well region and the second N+ doped region and further interposed between the gate structure and the P-type well region.

### Claim 11 (depends on 10)

The method of claim 10, further comprising providing an N-type layer and a P-top layer disposed adjacent to the N-type well region, the N-type layer being interposed between the third FOX portion and the P-top portion.

### Claim 12 (depends on 10)

The method of claim 10, further comprising providing an additional P-type well region disposed adjacent to the N-type well region and interposed between the first FOX portion and the P-type substrate.

### Claim 13 (depends on 8)

The method of claim 8, wherein a source of a junction gate field-effect transistor (JFET) is associated with the first N+ doped region, a drain of the JFET is associated with the second N+ doped region, a gate of the JFET is associated with the P+ doped region and the third N+ doped region, a source of an n-channel metal-oxide field effect transistor (NMOS) is associated with the P+ doped region and the third N+ doped region, and a drain of the NMOS is associated with the second N+ doped region.

### Claim 14

A semiconductor device comprising:
a P-type substrate;
an N-type well region disposed adjacent to the substrate;
a first P-type well region disposed adjacent to the N-type well region,
a second P-type well region disposed adjacent to the N-type well region and the substrate, the N-type well region encompassing the first P-type well region such that at least a portion of the N-type well region is interposed between the first and second P-type well regions; and
first and second N+ doped regions disposed adjacent to the N-type well region and on opposing sides of the first P-type well region;
wherein the second P-type well region comprises a second P+ doped region and the first P-type well region comprises a first P+ doped region, a third N+ doped region and a gate structure, the third N+ doped region being interposed between the P+ doped region and the gate structure; and
further wherein at least a portion of the second P-type well region is interposed between the first P+ doped region and the first N+ doped region.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further comprising a field oxide (FOX) portion disposed adjacent to the N-type well region and interposed between the first P-type well region and the second N+ doped region and further interposed between the gate structure and the first P-type well region.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, further comprising an N-type layer and a P-top layer disposed adjacent to the N-type well region, the N-type layer being interposed between the FOX portion and the P-top portion.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, further comprising a third P-type well region comprising a third P+ doped region, the third P-type well region being disposed adjacent to the N-type well region and the substrate such that at least a portion of the third P-type well region is interposed between the third P+ doped region and the first N+ doped region.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, wherein a source of a junction gate field-effect transistor (JFET) is associated with the first N+ doped region, a drain of the JFET is associated with the second N+ doped region, and a gate of the JFET is associated with the second P+ doped region.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein a source of an n-channel metal-oxide field effect transistor (NMOS) is associated with the first P+ doped region and the third N+ doped region and a drain of the NMOS is associated with the second N+ doped region.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, further comprising:
fourth, fifth, sixth, and seventh P-type well regions respectively comprising fourth, fifth, sixth, and seventh P+ doped regions; and
fourth, fifth, sixth, and seventh N+ doped regions disposed adjacent to the N-type well region, the fourth, fifth, sixth, and seventh N+ doped regions being disposed on an opposing side of the second P-type region from the second N+ doped region;
wherein the fourth N+ doped region is interposed between the second and fourth P-type well regions, the fifth N+ doped region is interposed between the fourth and fifth P-type well regions, the sixth N+ doped region is interposed between the fifth and sixth P-type well regions, and the seventh N+ doped region is interposed between the sixth and seventh P-type well regions.