# US 8,785,987 B2 · IGFET device having an RF capability

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- Number: US 8,785,987 B2
- Document ID: US8785987B2
- Status: Granted
- Kind: B2
- Application number: 13/189,342
- Filed: 2011-07-22
- Published: 2011-11-17
- Granted: 2014-07-22
- Earliest claimed: 2011-07-22
- Assignees: ACCO Corporation
- Applicants: Denis Masliah
- Inventors: Denis Masliah
- Web page: https://patentgrep.com/patent/US8785987B2

## CPC

- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 64/111: {Field plates}
- H10D 64/517: {characterised by the conducting layers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 84/151: {LDMOS having built-in components}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An IGFET device includes: —a semiconductor body having a major surface, —a source region of first conductivity type abutting the surface, —a drain region of the first conductivity-type abutting the surface and spaced from the source region with a channel therefrom, —an active gate overlying the channel and insulated from the channel by a first dielectric material forming the gate oxide of the IGFET device, —a dummy gate positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.

## Claims

### Claim 1

An IGFET device comprising:
a substrate;
two field oxide regions defined in the substrate and defining a device region therebetween;
a source region defined in the substrate within the device region;
a drain region also defined in the substrate within the device region and spaced from the source region by a channel region;
a first dielectric layer disposed on the substrate within a span of the device region;
an active gate insulated from the channel region by the first dielectric layer;
a dummy gate disposed on the first dielectric layer; and
a second dielectric material insulating the active gate from the dummy gate, the second dielectric material completely covering an entire top surface of the dummy gate, and the second dielectric material including an opening disposed therethrough to the active gate, the second dielectric material extending uninterrupted from the active gate to the dummy gate; and wherein the dummy gate, the active gate, and the second dielectric material disposed therebetween define a capacitor.

### Claim 2 (depends on 1)

The IGFET device of claim 1 wherein the active gate and the dummy gate each comprise a stack of the same conductive layers.

### Claim 3 (depends on 1)

The IGFET device of claim 1 wherein the dummy gate is disposed over the channel region.

### Claim 4 (depends on 1)

The IGFET device of claim 1 wherein the dummy gate is disposed over the drain region.

### Claim 5 (depends on 4)

The IGFET device of claim 4 wherein the drain region comprises a highly doped region of a first conductivity type located in contact with a low doped region of the first conductivity type.

### Claim 6 (depends on 5)

The IGFET device of claim 5 wherein the dummy gate is disposed over the low doped region of the drain region.

### Claim 7 (depends on 1)

The IGFET device of claim 1 wherein a first portion of the first dielectric layer insulates the active gate from the channel region and a second portion of the first dielectric layer insulates the dummy gate from the channel region and the first and second portions are disjoined.