# US 8,785,983 B2 · Solid-state image pickup device

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- Number: US 8,785,983 B2
- Document ID: US8785983B2
- Status: Granted
- Kind: B2
- Application number: 13/872,694
- Filed: 2013-04-29
- Published: 2013-09-19
- Granted: 2014-07-22
- Earliest claimed: 2004-02-04
- Assignees: Sony Corporation
- Applicants: Sony Corporation
- Inventors: Takayuki Ezaki; Teruo Hirayama
- Web page: https://patentgrep.com/patent/US8785983B2

## CPC

- H10F 39/8037: {the integrated elements comprising a transistor}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10F 39/014: {of CMOS image sensors}
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/199: {Back-illuminated image sensors}
- H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes}
- H10F 39/8053: {Colour filters}
- H10F 39/8063: {Microlenses}
- H10F 39/807: {Pixel isolation structures}
- H10F 77/00: Constructional details of devices covered by this subclass (constructional details of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00)
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.

## Claims

### Claim 1

A solid-state image pickup device comprising:
a pixel composed of a photodiode and a transistor; and
a semiconductor substrate with said pixel formed thereon,
wherein a pn junction portion formed between high concentration regions of said photodiode is formed within said semiconductor substrate and a part of said pn junction portion of said photodiode is extended to a lower portion of said transistor formed on the surface of said semiconductor substrate,
wherein said pixel includes a charge readout transistor for reading out signal electric charges from said photodiode, a channel portion of said charge readout transistor being formed in the depth direction of the surface of said semiconductor substrate.

### Claim 2 (depends on 1)

A solid-state image pickup device according to claim 1, wherein said charge readout transistor includes a gate electrode and a gate insulating film, the bottom portions of which are formed at the position deeper than the depth of said pn junction portion of said photodiode.

### Claim 3

An imaging device comprising:
a photodiode between a surface side of a semiconductor substrate and a back side of the semiconductor substrate, said photodiode including a first region of a first conductivity type and a second region of a second conductivity type; and
a charge readout transistor extending from the surface side of the semiconductor substrate to a depth reaching a portion of the second region, the first region being closer to the surface side of the semiconductor substrate than the second region,
wherein at least a bottom portion of the charge readout transistor touches a third region of the first conductivity type.

### Claim 4 (depends on 3)

The device of claim 3, further comprising:
a floating diffusion region adjacent to the charge readout transistor at the surface side of the semiconductor substrate.

### Claim 5 (depends on 3)

The device of claim 3, wherein the charge readout transistor includes a gate electrode and a gate insulating film formed in a groove.

### Claim 6 (depends on 5)

The device of claim 5, wherein at least the bottom portion and a portion of sidewalls of the groove are surrounded by the third region.

### Claim 7 (depends on 6)

The device of claim 6, wherein the third region has lower impurity concentration of the first conductivity type than that of the first region.

### Claim 8 (depends on 3)

The device of claim 3, wherein the back side of the semiconductor substrate is a light incident side.

### Claim 9 (depends on 3)

The device of claim 3, further comprising:
a reset transistor and an amplifying transistor.

### Claim 10 (depends on 3)

The device of claim 3, wherein the first conductivity type is a p-type and the second conductivity type is an n-type.