# US 8,785,974 B2 · Bumped, self-isolated GaN transistor chip with electrically isolated back surface

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- Number: US 8,785,974 B2
- Document ID: US8785974B2
- Status: Granted
- Kind: B2
- Application number: 12/756,975
- Filed: 2010-04-08
- Published: 2010-10-14
- Granted: 2014-07-22
- Earliest claimed: 2009-04-08
- Assignees: Efficient Power Conversion Corporation
- Applicants: Alexander Lidow; Robert Beach; Alana Nakata; Jianjun Cao
- Inventors: Alexander Lidow; Robert Beach; Alana Nakata; Jianjun Cao
- Web page: https://patentgrep.com/patent/US8785974B2

## CPC

- H10W 74/147: {the encapsulations being multilayered}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/82: Heterojunctions
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10W 40/226: {characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461)}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 74/134: {the encapsulations being in grooves in the semiconductor body}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.

## Claims

### Claim 1

A semiconductor device comprising:
a silicon substrate;
a compound semiconductor material including an active area;
an insulating material between the silicon substrate and the active area; and
a top surface comprising:
means of electrical connection to the active area, and
a first passivation material, wherein the passivation material is silicon nitride, silicon dioxide, or a combination of both, and
wherein the electrical connection includes at least one gate electrode, at least one drain electrode, and at least two source electrodes, wherein one of the source electrodes is used as a Kelvin connection.

### Claim 2 (depends on 1)

The device of claim 1, wherein the compound material is formed of various layers comprised of a combination of Indium, Gallium, Nitrogen, and Aluminum.

### Claim 3 (depends on 1)

The device of claim 1, wherein the device is an enhancement mode transistor.

### Claim 4 (depends on 2)

The device of claim 2, wherein the device is an enhancement mode GaN transistor.

### Claim 5 (depends on 1)

The device of claim 1, further comprising a second passivation material of polyimide plastic.

### Claim 6 (depends on 1)

The device of claim 1, wherein the active area does not extend to the edges of the device.

### Claim 7 (depends on 1)

The device of claim 1, further comprising a heatsink mounted directly to a second surface of the silicon substrate without a layer of insulation between the substrate and the heat sink.

### Claim 8 (depends on 1)

The device of claim 1, wherein the electrical connection further comprises a solder bump formed of various combinations of copper, lead, silver, antimony and tin.

### Claim 9 (depends on 3)

The device of claim 3, wherein multiple active devices are integrated onto the silicon substrate.

### Claim 10 (depends on 3)

The device of claim 3, wherein the transistors are in a half bridge or a full bridge configuration.

### Claim 11 (depends on 3)

The device of claim 3, wherein the transistors are driven by smaller driver transistors on the same silicon substrate.