# US 8,785,966 B2 · Magnetic tunnel junction transistor devices

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- Number: US 8,785,966 B2
- Document ID: US8785966B2
- Status: Granted
- Kind: B2
- Application number: 13/115,241
- Filed: 2011-05-25
- Published: 2012-11-29
- Granted: 2014-07-22
- Earliest claimed: 2011-05-25
- Assignees: International Business Machines Corporation
- Applicants: Daniel Christopher Worledge; Vladislav Korenivski
- Inventors: Daniel Christopher Worledge; Vladislav Korenivski
- Web page: https://patentgrep.com/patent/US8785966B2

## CPC

- H10B 61/22: {of the field-effect transistor [FET] type}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1675: {Writing or programming circuits or methods}
- H10B 61/20: {comprising components having three or more electrodes, e.g. transistors}
- H10N 50/10: Magnetoresistive devices
- H10B: ELECTRONIC MEMORY DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Magnetic tunnel junction transistor devices and methods for operating and forming magnetic tunnel junction transistor devices. In one aspect, a magnetic tunnel junction transistor device includes a first source/drain electrode, a second source/drain electrode, a gate electrode, and a magnetic tunnel junction disposed between the gate electrode and the second source/drain electrode. The magnetic tunnel junction includes a magnetic free layer that extends along a length of the gate electrode toward the first source/drain electrode such that an end portion of the magnetic free layer is disposed between the gate electrode and the first source/drain electrode. The magnetic tunnel junction transistor device switches a magnetization orientation of the magnetic free layer by application of a gate voltage to the gate electrode, thereby changing a resistance between the first and second source/drain electrodes through the magnetic free layer.

## Claims

### Claim 1

A magnetic tunnel junction transistor device, comprising:
a first source/drain electrode;
a second source/drain electrode;
a gate electrode; and
a magnetic tunnel junction disposed between the gate electrode and the second source/drain electrode, the magnetic tunnel junction comprising a magnetic free layer that extends along a length of the gate electrode toward the first source/drain electrode such that an end portion of the magnetic free layer is disposed between the gate electrode and the first source/drain electrode,
wherein a voltage applied to the gate electrode changes a magnetization orientation of the magnetic free layer.

### Claim 2 (depends on 1)

The transistor device of claim 1, wherein the magnetic tunnel junction is a single magnetic tunnel junction structure.

### Claim 3 (depends on 1)

The transistor device of claim 1, wherein the magnetic tunnel junction is a double magnetic tunnel junction structure.

### Claim 4 (depends on 1)

The transistor device of claim 1, further comprising a gate dielectric layer interposed between the gate electrode and the magnetic free layer.

### Claim 5 (depends on 4)

The transistor device of claim 4, wherein the gate dielectric layer is formed of MgO.

### Claim 6 (depends on 1)

The transistor device of claim 1, wherein the first and second source/drain electrodes and the gate electrode are formed of tantalum.

### Claim 7 (depends on 1)

The transistor device of claim 1, wherein the magnetic tunnel junction further comprises:
a first tunnel barrier layer formed on a portion of the magnetic free layer;
a resonant tunneling layer formed on the first tunnel barrier layer;
a second tunnel barrier layer formed on the resonant tunneling layer; and
a first magnetic pinned layer formed on the second tunnel barrier layer.

### Claim 8 (depends on 7)

The transistor device of claim 7, wherein the first and second tunnel barriers are formed of MgO.

### Claim 9 (depends on 7)

The transistor device of claim 7, wherein the resonant tunneling layer is formed of Vanadium.

### Claim 10 (depends on 7)

The transistor device of claim 7, wherein the first magnetic pinned layer is formed of a magnetic material including at least one of cobalt (Co), or iron (Fe), or any combination thereof.

### Claim 11 (depends on 7)

The transistor device of claim 7, wherein the magnetic tunnel junction further comprises:
a coupling layer formed on the first magnetic pinned layer;
a second magnetic pinned layer formed on the coupling layer;
an antiferromagnetic layer formed on the second magnetic pinned layer.

### Claim 12 (depends on 11)

The transistor device of claim 11, wherein the coupling layer is formed of Ru.

### Claim 13 (depends on 11)

The transistor device of claim 11, wherein the second magnetic pinned layer is formed of a magnetic material including at least one of cobalt (Co), or iron (Fe), or any combination thereof.

### Claim 14 (depends on 11)

The transistor device of claim 11, wherein the antiferromagnetic layer is formed of PtMn.

### Claim 15

A magnetic tunnel junction transistor device comprising:
a first source/drain electrode;
a second source/drain electrode;
a gate electrode; and
a double magnetic tunnel junction disposed between the gate electrode and the second source/drain electrode, the double magnetic tunnel junction comprising:
a magnetic free layer that extends along a length of the gate electrode toward the first source/drain electrode such that an end portion of the magnetic free layer is disposed between the gate electrode and the first source/drain electrode, wherein a voltage applied to the gate electrode changes a magnetization orientation of the magnetic free layer;
a first MgO tunnel barrier layer formed on a portion of the magnetic free layer below the second source/drain electrode;
a resonant tunneling layer formed on the first MgO tunnel barrier layer;
a second MgO tunnel barrier layer formed on the resonant tunneling layer;
a CoFeB magnetic pinned layer formed on the second MgO tunnel barrier layer;
a coupling layer formed on the CoFeB magnetic pinned layer;
a CoFe magnetic pinned layer formed on the coupling layer; and
an antiferromagnetic layer formed on the CoFe magnetic pinned layer.

### Claim 16 (depends on 15)

The transistor device of claim 15, further comprising a gate dielectric layer interposed between the gate electrode and the magnetic free layer.

### Claim 17 (depends on 16)

The transistor device of claim 16, wherein the gate dielectric layer is formed of MgO with a thickness of about 3 nm.

### Claim 18 (depends on 16)

The transistor device of claim 16, wherein the first and second source/drain electrodes and the gate electrode are formed of tantalum.

### Claim 19 (depends on 16)

The transistor device of claim 16, wherein the resonant tunneling layer is formed of Vanadium with a thickness of about 1 nm.

### Claim 20

A method for operating a magnetic tunnel junction transistor device having a first source/drain electrode, a second source/drain electrode, a gate electrode, and a magnetic tunnel junction disposed between the gate electrode and the second source/drain electrode, wherein the magnetic tunnel junction comprises a magnetic free layer that extends along a length of the gate electrode toward the first source/drain electrode such that an end portion of the magnetic free layer is disposed between the gate electrode and the first source/drain electrode, the method comprising:
switching a magnetization orientation of the magnetic free layer by application of a gate voltage to the gate electrode, thereby changing a resistance between the first and second source/drain electrodes through the magnetic free layer.

### Claim 21 (depends on 20)

The method of claim 20, wherein the transistor device switches between an On state and an Off state based on the gate voltage applied to the gate electrode.

### Claim 22 (depends on 21)

The method of claim 21, wherein the gate voltage ranges between approximately 0 millivolts (mV) to approximately 100 (mV).

### Claim 23 (depends on 21)

The method of claim 21, wherein when the transistor device is in the Off state, a magnetization orientation of the magnetic free layer is in plane with, and antiparallel to, a magnetization orientation of a magnetic pinned layer of the magnetic tunnel junction such that the resistance between the first and second source/drain electrodes through the magnetic free layer is in a high resistance state.

### Claim 24 (depends on 21)

The method of claim 21, wherein when the transistor device is in the On state, a magnetization orientation of the magnetic free layer is perpendicular to a magnetization orientation of a magnetic pinned layer of the magnetic tunnel junction such that the resistance between the first and second source/drain electrodes through the magnetic free layer is in a low resistance state.

### Claim 25

A semiconductor integrated circuit, comprising a plurality of magnetic tunnel junction transistor devices formed on a bulk substrate, each of the magnetic tunnel junction transistor devices comprising:
a first source/drain electrode;
a second source/drain electrode;
a gate electrode; and
a magnetic tunnel junction disposed between the gate electrode and the second source/drain electrode, the magnetic tunnel junction comprising a magnetic free layer that extends along a length of the gate electrode toward the first source/drain electrode such that an end portion of the magnetic free layer is disposed between the gate electrode and the first source/drain electrode,
wherein a voltage applied to the gate electrode changes a magnetization orientation of the magnetic free layer.