# US 8,785,956 B2 · Chip package having optical-electronic device with plurality of light shielding layers and substrate through-hole with void, and method for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,956 B2 - Document ID: US8785956B2 - Status: Granted - Kind: B2 - Application number: 13/560,842 - Filed: 2012-07-27 - Published: 2013-01-31 - Granted: 2014-07-22 - Earliest claimed: 2011-07-29 - Applicants: Chuan-Jin Shiu; Po-Shen Lin; Yi-Ming Chang; Hui-Ching Yang; Chiung-Lin Lai - Inventors: Chuan-Jin Shiu; Po-Shen Lin; Yi-Ming Chang; Hui-Ching Yang; Chiung-Lin Lai - Web page: https://patentgrep.com/patent/US8785956B2 ## CPC - H10F 39/8057: {Optical shielding} - H10F 39/018: {of hybrid image sensors} - H10F 39/026: {Wafer-level processing} - H10F 39/804: {Containers or encapsulations} - H10F 39/809: {of hybrid image sensors} - H10F 39/811: {Interconnections} - H10H 20/852: Encapsulations - H10W 70/65: Shapes or dispositions of interconnections - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/29: Bond pads specially adapted therefor - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a conducting layer disposed on the substrate, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a first light shielding layer disposed on the second surface of the substrate; and a second light shielding layer disposed on the first light shielding layer and directly contacting with the first light shielding layer, wherein a contact interface is between the first light shielding layer and the second light shielding layer. ## Claims ### Claim 1 A chip package, comprising: a substrate having a first surface and a second surface; an optoelectronic device formed in the substrate; a through-hole extending from the second surface to the first surface; a conducting layer disposed on the substrate, having a portion overlying both sidewalls and a bottom of the through-hole, wherein the conducting layer is electrically connected to the optoelectronic device; an insulating layer disposed between the substrate and the conducting layer; a first light shielding layer disposed on the second surface of the substrate; and a second light shielding layer disposed on the first light shielding layer and directly contacting with the first light shielding layer, wherein a contact interface is between the first light shielding layer and the second light shielding layer, wherein the through-hole is partially filled with the first light shielding layer such that a void is formed between the bottom of the through-hole and the first light shielding layer in the through-hole, and wherein the portion of the conducting layer, which overlies both sidewalls and the bottom of the through-hole, directly contacts the void. ### Claim 2 (depends on 1) The chip package as claimed in claim 1, further comprising a conducting bump disposed on the second surface of the substrate and electrically contacting with the conducting layer. ### Claim 3 (depends on 1) The chip package as claimed in claim 1, further comprising a protection layer disposed between the second surface of the substrate and the first light shielding layer. ### Claim 4 (depends on 3) The chip package as claimed in claim 3, further comprising a conducting bump disposed on the second surface of the substrate and penetrating through the protection layer to electrically contact with the conducting layer. ### Claim 5 (depends on 1) The chip package as claimed in claim 1, further comprising a through-hole extending from the second surface towards the first surface, wherein the insulating layer extends on a sidewall of the through-hole and extends on the second surface of the substrate, and the conducting layer extends on the insulating layer in the through-hole. ### Claim 6 (depends on 1) The chip package as claimed in claim 1, further comprising a transparent substrate disposed on the first surface of the substrate. ### Claim 7 (depends on 6) The chip package as claimed in claim 6, further comprising a spacer layer disposed between the substrate and the transparent substrate, wherein the spacer layer, the substrate, and the transparent substrate together surround a cavity on the optoelectronic device. ### Claim 8 (depends on 1) The chip package as claimed in claim 1, wherein the material of the first light shielding layer and the material of the second light shielding layer are the same. ### Claim 9 (depends on 1) The chip package as claimed in claim 1, further comprising at least one third light shielding layer disposed on the second light shielding layer. ### Claim 10 (depends on 9) The chip package as claimed in claim 9, wherein the at least one third light shielding layer directly contacts with the second light shielding layer. ### Claim 11 A method for forming a chip package, comprising: providing a substrate having a first surface and a second surface, wherein at least one optoelectronic device is formed in the substrate; forming a through-hole in the substrate; forming an insulating layer on the substrate; forming a conducting layer on the insulating layer on the substrate, having a portion overlying both sidewalls and a bottom of the through-hole, wherein the conducting layer is electrically connected to the at least one optoelectronic device; forming a first light shielding layer on the second surface of the substrate and partially filling the through-hole with the first light shielding layer such that a void is formed between the bottom of the through-hole and the first light shielding layer in the through-hole; and forming a second light shielding layer on the first light shielding layer, wherein the second light shielding layer directly contacts with the first light shielding layer, and a contact interface is between the first light shielding layer and the second light shielding layer, and wherein the portion of the conducting layer, which overlies both sidewalls and the bottom of the through-hole, directly contacts the void. ### Claim 12 (depends on 11) The method for forming a chip package as claimed in claim 11, wherein the step of forming the first light shielding layer comprises: applying a polymer solution on the second surface of the substrate to form a light shielding material layer; and performing an exposure process and a development process to the light shielding material layer to form the first light shielding layer. ### Claim 13 (depends on 12) The method for forming a chip package as claimed in claim 12, further comprising hardening the first light shielding layer before the second light shielding layer is formed. ### Claim 14 (depends on 13) The method for forming a chip package as claimed in claim 13, wherein the step of hardening the first light shielding layer comprises performing a heating process to the first light shielding layer. ### Claim 15 (depends on 14) The method for forming a chip package as claimed in claim 14, wherein the heating process comprises elevating the temperature of the first light shielding layer to be between about 150° C. and 250° C. and then maintaining the temperature for about 15 minutes and about 1 hour. ### Claim 16 (depends on 14) The method for forming a chip package as claimed in claim 14, wherein the step of forming the second light shielding layer comprises: applying a second polymer solution on the first light shielding layer after hardening to form a second light shielding material layer; and performing an exposure process and a development process to the second light shielding material layer to form the second light shielding layer. ### Claim 17 (depends on 16) The method for forming a chip package as claimed in claim 16, further comprising hardening the second light shielding layer, wherein the step of hardening the second light shielding layer comprises performing a heating process to the second light shielding layer. ### Claim 18 (depends on 11) The method for forming a chip package as claimed in claim 11, further comprising forming a third light shielding layer on the second light shielding layer. ### Claim 19 (depends on 11) The method for forming a chip package as claimed in claim 11, further comprising: forming a protection layer between the substrate and the light shielding layer; and planarizing the protection layer before the first light shielding layer is formed. ### Claim 20 (depends on 11) The method for forming a chip package as claimed in claim 11, further comprising performing a dicing process along a plurality of predetermined scribe lines of the substrate to form a plurality of chip packages separated from each other.