# US 8,785,930 B2 · Method for indexing dies comprising integrated circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,930 B2 - Document ID: US8785930B2 - Status: Granted - Kind: B2 - Application number: 12/649,243 - Filed: 2009-12-29 - Published: 2010-07-01 - Granted: 2014-07-22 - Earliest claimed: 2008-12-30 - Assignees: STMicroelectronics S.r.l. - Applicants: Daniele Alfredo Brambilla; Fausto Redigolo - Inventors: Daniele Alfredo Brambilla; Fausto Redigolo - Web page: https://patentgrep.com/patent/US8785930B2 ## CPC - H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes} - G01R 19/0092: {Measuring current only} - H10D 1/47: Resistors having no potential barriers - H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes} - H10W 46/401: {for identification or tracking} - H10W 46/403: {for non-wireless electrical read out} - H10W 46/603: {Formed on wafers or substrates before dicing and remaining on chips after dicing} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Indexing a plurality of die obtainable from a material wafer comprising a plurality of stacked material layers. Each die is obtained in a respective position of the wafer. A manufacturing stage comprises at least two steps for treating a respective superficial portion of the material wafer that corresponds to a subset of said plurality of dies using the at least one lithographic mask through the exposition to the proper radiation in temporal succession. The method may include providing a die index on each die which is indicative of the position of the respective die by forming an external index indicative of the position of the superficial portion of the material wafer corresponding to the subset of the plurality of dies including said die and may comprise a plurality of electronic components electrically coupled to each other by means of a respective common control line. ## Claims ### Claim 1 A semiconductor die, comprising: a first circuit having a first structure indicative of a region of a wafer and an electronic structure configured to store a value indicative of the region of the wafer corresponding to the die such that, when read, a first signal is generated corresponding to the region; and a second structure configured to identify a section of the region corresponding to the die. ### Claim 2 (depends on 1) The semiconductor die of claim 1 wherein the first signal comprises a first voltage. ### Claim 3 (depends on 1) The semiconductor die of claim 1 wherein the first signal comprises a current. ### Claim 4 (depends on 1) The semiconductor die of claim 1 wherein the value comprises an amplitude. ### Claim 5 (depends on 1) The semiconductor die of claim 1 wherein the value comprises a phase. ### Claim 6 (depends on 1) The semiconductor die of claim 1 wherein the region comprises a region of the wafer currently occupied by the die. ### Claim 7 (depends on 1) The semiconductor die of claim 1 wherein the region comprises a region of the wafer from which the die was previously obtained. ### Claim 8 (depends on 1) The semiconductor die of claim 1 wherein the region comprises multiple sections. ### Claim 9 (depends on 1) The semiconductor die of claim 1 wherein the first structure comprises a second circuit configured to generate a second signal having a second characteristic that identifies the section of the region. ### Claim 10 (depends on 1) The semiconductor die of claim 1 wherein the first structure is configured to identify the section in a manner that is visually perceivable. ### Claim 11 (depends on 1) The semiconductor die of claim 1, further comprising: wherein the first circuit is configured to generate the first signal having a first characteristic that identifies a first coordinate of the wafer region; and a second circuit configured to generate a second signal having a second characteristic that identifies a second coordinate of the wafer region. ### Claim 12 (depends on 1) The semiconductor die of claim 1 wherein the first circuit comprises a plurality of components, at least some of which are configured to cooperate to generate the first signal. ### Claim 13 (depends on 1) The semiconductor die of claim 1 wherein the first circuit comprises a plurality of parallel-coupled transistors that are configured to cooperate to generate the first signal. ### Claim 14 (depends on 1) The semiconductor die of claim 1 wherein the first circuit comprises a plurality of parallel-coupled transistors, at least some of the transistors configured to conduct a first current, and at least some of the other transistors configured to conduct approximately a second current that is significantly smaller than the first current, the first signal including at least the first current. ### Claim 15 (depends on 1) The semiconductor die of claim 1 wherein the first circuit comprises a plurality of parallel-coupled transistors, at least some of the transistors configured to conduct a current, and at least some of the other transistors configured to conduct approximately zero current, the first signal including at least the current. ### Claim 16 An integrated circuit, comprising: a package; and a semiconductor die disposed within the package and including a first circuit having a first structure indicative of a region of a wafer and an electronic structure configured to store a value indicative of the region of the wafer corresponding to the die such that, when read, a first signal is generated corresponding to the region; and a first structure configured to identify a section of the region corresponding to the die. ### Claim 17 (depends on 16) The integrated circuit of claim 16 wherein the package further comprises a pin that is configured to carry the first signal. ### Claim 18 (depends on 16) The integrated circuit of claim 16 wherein: the first structure comprises a second circuit configured to generate a second signal having a second characteristic that identifies the section of the region; and the package comprises a first pin that is configured to carry the first signal and a second pin that is operable to carry the second signal. ### Claim 19 (depends on 16) The integrated circuit of claim 16 wherein: the first circuit is configured to generate the first signal having a first characteristic that identifies a first coordinate of the wafer region; and the die comprises a second circuit configured to generate a second signal having a second characteristic that identifies a second coordinate of the wafer region; and the package includes first and second pins respectively configured to carry the first and second signals. ### Claim 20 A system, comprising: a first integrated circuit, comprising: a first package; and a first semiconductor die disposed within the package and including a first circuit having a first structure indicative of a region of a wafer and an electronic structure configured to store a value indicative of the region of the wafer corresponding to the die such that, when read, a first signal is generated corresponding to the region; and a first structure configured to identify a section of the region corresponding to the die; and a second integrated circuit coupled to the first integrated circuit. ### Claim 21 (depends on 20) The system of claim 20 wherein the second integrated circuit is disposed on the die. ### Claim 22 (depends on 20) The system of claim 20 wherein the second integrated circuit is disposed within the package. ### Claim 23 (depends on 20) The system of claim 20 wherein the second integrated circuit is disposed on a second die. ### Claim 24 (depends on 20) The system of claim 20 wherein the second integrated circuit is disposed within a second package. ### Claim 25 (depends on 20) The system of claim 20 wherein at least one of the first and second integrated circuits comprises a controller. ### Claim 26 A semiconductor die, comprising: a first index configured to store an electronically readable value indicative of a region of a wafer corresponding to the die and having a structure that physically indicates the region of the wafer; and a second index configured to identify a section of the region corresponding to the die. ### Claim 27 (depends on 26) The semiconductor die of claim 26, wherein a second index is further configured to store an electronically readable value indicative of the section of the region. ### Claim 28 (depends on 26) The semiconductor die of claim 26, wherein the first and second indexes comprise transistors. ### Claim 29 A semiconductor die, comprising: a first physical index indicative of a position of a mask with respect to a wafer from which the die was obtained during manufacture of the die; a second physical index indicative of a position of the mask with respect to the die during manufacture of the die; and an electronic index configured to store information about the first and second physical indexes. ### Claim 30 (depends on 29) The semiconductor die of claim 29 wherein the first physical index and the electronic index comprise the same structure. ### Claim 31 (depends on 29) The semiconductor die of claim 29 wherein the second physical index and the electronic index comprise the same structure.