# US 8,785,912 B2 · Graphene electronic device including a plurality of graphene channel layers

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- Number: US 8,785,912 B2
- Document ID: US8785912B2
- Status: Granted
- Kind: B2
- Application number: 13/225,988
- Filed: 2011-09-06
- Published: 2012-07-05
- Granted: 2014-07-22
- Earliest claimed: 2010-12-29
- Assignees: Samsung Electronics Co., Ltd.; Snu R&Db Foundation
- Applicants: Hyun-jong Chung; Jae-hong Lee; Jae-ho Lee; Hyung-cheol Shin; Sun-ae Seo; Sung-hoon Lee; Jin-seong Heo; Hee-jun Yang
- Inventors: Hyun-jong Chung; Jae-hong Lee; Jae-ho Lee; Hyung-cheol Shin; Sun-ae Seo; Sung-hoon Lee; Jin-seong Heo; Hee-jun Yang
- Web page: https://patentgrep.com/patent/US8785912B2

## CPC

- H10D 62/882: {Graphene}
- H10D 30/01: Manufacture or treatment
- H10D 30/017: {of FETs having two-dimensional material channels, e.g. TMD FETs}
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/8303: {Diamond}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Graphene electronic devices may include a gate electrode on a substrate, a first gate insulating film covering the gate electrode, a plurality of graphene channel layers on the substrate, a second gate insulating film between the plurality of graphene channel layers, and a source electrode and a drain electrode connected to both edges of each of the plurality of graphene channel layers.

## Claims

### Claim 1

A graphene electronic device comprising:
a gate electrode on a substrate;
a first gate insulating film on the substrate to cover the gate electrode;
a plurality of graphene channel layers on the first gate insulating film;
a second gate insulating film between the plurality of the graphene channel layers;
a source electrode directly connected to one edge of each of the plurality of the graphene channel layers; and
a drain electrode directly connected to another edge of each of the plurality of the graphene channel layers,
wherein the plurality of the graphene channel layers includes a first graphene channel layer on the first gate insulating film and a second graphene channel layer on the second gate insulating film, the second gate insulating film is on the first graphene channel, and each of the first graphene channel layer and the second graphene channel layer has a width in a range of 1 nm to 20 nm, and
wherein the first graphene channel layer has a length greater than that of the second graphene channel layer.

### Claim 2 (depends on 1)

The graphene electronic device of claim 1, wherein the gate electrode is embedded in the substrate and an upper surface of the gate electrode contacts the first gate insulating film.

### Claim 3 (depends on 1)

The graphene electronic device of claim 1, wherein the substrate is a conductive substrate.

### Claim 4 (depends on 1)

The graphene electronic device of claim 1, wherein the second gate insulating film has a thickness in a range from about 10 nm to about 200 nm.

### Claim 5 (depends on 1)

The graphene electronic device of claim 1, wherein the source electrode is formed on the first and second graphene channel layers to contact the one edge of each of the first and second graphene channel layers, and the drain electrode is formed on the first and second graphene channel layers to contact the other edge of each of the first and second graphene channel layers.

### Claim 6 (depends on 1)

The graphene electronic device of claim 1, wherein the second gate insulating film is formed of a material selected from the group consisting of silicon oxide, silicon nitride, hafnium oxide, and aluminum oxide.

### Claim 7 (depends on 1)

The graphene electronic device of claim 1, wherein the first graphene channel layer and the second graphene channel layer are separated from each other in a direction vertical to the substrate and parallel to each other in a length direction of the substrate.

### Claim 8

A graphene electronic device comprising:
an insulating layer covering a substrate;
a plurality of graphene channel layers on the substrate;
a source electrode connected to one edge of each of the plurality of the graphene channel layers;
a drain electrode connected to another edge of each of the plurality of the graphene channel layers;
a first gate insulating film covering the plurality of the graphene channel layers between the source electrode and the drain electrode;
a second gate insulating film between the plurality of the graphene channel layers; and
a gate electrode on the first gate insulating film,
wherein the plurality of graphene channel layers includes a first graphene channel layer on the second gate insulating film and a second graphene channel layer on the insulating layer, the second gate insulating film is on the second graphene channel layer, and each of the first graphene channel layer and the second graphene channel layer has a width in a range of 1 nm to 20 nm, and
wherein the second graphene channel layer has a length greater than that of the first graphene channel layer.

### Claim 9 (depends on 8)

The graphene electronic device of claim 8, wherein the second gate insulating film has a thickness in a range from about 10 nm to about 200 nm.

### Claim 10 (depends on 8)

The graphene electronic device of claim 8, wherein the source electrode is formed on the first and second graphene channel layers to contact the one edge of each of the first and second graphene channel layers, and the drain electrode is formed on the first and second graphene channel layers to contact the other edge of each of the first and second graphene channel layers.

### Claim 11 (depends on 8)

The graphene electronic device of claim 8, wherein the second gate insulating film is formed of a material selected from the group consisting of silicon oxide, silicon nitride, hafnium oxide, and aluminum oxide.

### Claim 12 (depends on 8)

The graphene electronic device of claim 8, wherein the first graphene channel layer and the second graphene channel layer are separated from each other in a direction vertical to the substrate and parallel to each other in a length direction of the substrate.