# US 8,785,911 B2 · Graphene or carbon nanotube devices with localized bottom gates and gate dielectric

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- Number: US 8,785,911 B2
- Document ID: US8785911B2
- Status: Granted
- Kind: B2
- Application number: 13/167,570
- Filed: 2011-06-23
- Published: 2012-12-27
- Granted: 2014-07-22
- Earliest claimed: 2011-06-23
- Assignees: International Business Machines Corporation
- Applicants: Zhihong Chen; Aaron Daniel Franklin; Shu-Jen Han; James Bowler Hannon; Katherine L. Saenger; George Stojan Tulevski
- Inventors: Zhihong Chen; Aaron Daniel Franklin; Shu-Jen Han; James Bowler Hannon; Katherine L. Saenger; George Stojan Tulevski
- Web page: https://patentgrep.com/patent/US8785911B2

## CPC

- H10D 30/472: {having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 30/00: Nanotechnology for materials or surface science, e.g. nanocomposites
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 62/357: {of FETs}
- H10D 62/882: {Graphene}
- H10K 71/621: {Providing a shape to conductive layers, e.g. patterning or selective deposition}
- H10K 10/466: {Lateral bottom-gate IGFETs comprising only a single gate}
- H10K 10/481: {characterised by the gate conductors}
- H10K 85/221: {Carbon nanotubes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

Transistor devices having nanoscale material-based channels (e.g., carbon nanotube or graphene channels) and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; an insulator on the substrate; a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator; a local gate dielectric on the bottom gate; a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

## Claims

### Claim 1

A transistor device, comprising:
a substrate;
an insulator on the substrate;
a local bottom gate embedded in the insulator, wherein a top surface of the gate is substantially coplanar with a surface of the insulator;
a local gate dielectric on the bottom gate;
a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and
conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

### Claim 2 (depends on 1)

The device of claim 1, wherein the carbon-based nanostructure material comprises a graphene or carbon nanotube layer.

### Claim 3 (depends on 1)

The device of claim 1, wherein the insulator comprises silicon dioxide.

### Claim 4 (depends on 1)

The device of claim 1, wherein the local bottom gate comprises a conductive material selected from the group consisting of doped polycrystalline silicon, doped single-crystal silicon, at least one metal and a layered stack of conductive materials.

### Claim 5 (depends on 1)

The device of claim 1, wherein the local gate dielectric comprises a material selected from the group consisting of an insulating oxide, an insulating nitride, an insulating oxynitride, and combinations comprising at least one of the foregoing materials in a layered configuration.

### Claim 6 (depends on 1)

The device of claim 1, further comprising:
a blanket gate dielectric on the local gate dielectric and at least a portion of the insulator.

### Claim 7 (depends on 4)

The device of claim 4, wherein the local bottom gate comprises palladium, and wherein the local gate dielectric comprises titanium oxide.

### Claim 8 (depends on 5)

The device of claim 5, wherein the local gate dielectric comprises silicon dioxide.

### Claim 9 (depends on 6)

The device of claim 6, wherein the local gate dielectric comprises silicon dioxide and the blanket gate dielectric comprises a metal oxide.

### Claim 10

A method of fabricating a transistor device, comprising the steps of:
providing a substrate having an insulator thereon;
forming a local bottom gate in a trench in the insulator;
forming a local gate dielectric on the bottom gate;
forming a carbon-based nanostructure material over at least a portion of the local gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and
forming conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

### Claim 11 (depends on 10)

The method of claim 10, further comprising the step of:
etching the trench in the insulator through a patterned resist layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein the step of forming the local gate dielectric on the bottom gate comprises the step of:
oxidizing an upper portion of the bottom gate to form an oxide dielectric.

### Claim 13 (depends on 10)

The method of claim 10, further comprising the step of:
forming a blanket gate dielectric on the local gate dielectric and at least a portion of the insulator.

### Claim 14 (depends on 11)

The method of claim 11, wherein the step of forming the bottom-gate in the trench comprises the steps of:
blanket depositing a gate material onto the patterned resist layer and into the trench; and
removing the patterned resist layer and the gate material outside of the trench.

### Claim 15 (depends on 11)

The method of claim 11, further comprising the steps of:
blanket depositing a gate material onto the patterned resist layer and into the trench;
blanket depositing a gate dielectric material onto the gate material; and
removing the patterned resist layer along with portions of the gate material and portions of the gate dielectric material outside of the trench.

### Claim 16

A method of fabricating a transistor device, comprising the steps of:
providing a wafer having a layer of electrically conductive material on an insulating layer;
forming cavities in the wafer to isolate one or more portions of the conductive material, wherein an isolated portion of the conductive material serves as a local bottom gate of the device;
filling the cavities with a dielectric;
forming a gate dielectric on the bottom gate;
forming a carbon-based nanostructure material over at least a portion of the gate dielectric, wherein a portion of the carbon-based nanostructure material serves as a channel of the device; and
forming conductive source and drain contacts to one or more portions of the carbon-based nanostructure material on opposing sides of the channel that serve as source and drain regions of the device.

### Claim 17 (depends on 16)

The method of claim 16, wherein the layer of conductive material comprises a single crystal semiconductor-on-insulator layer and the insulating layer comprises a buried oxide.

### Claim 18 (depends on 16)

The method of claim 16, wherein the layer of conductive material comprises doped polycrystalline silicon.

### Claim 19 (depends on 16)

The method of claim 16, wherein the cavities extend into the insulating layer.

### Claim 20 (depends on 16)

The method of claim 16, wherein the cavities extend through the insulating layer.

### Claim 21 (depends on 16)

The method of claim 16, wherein the gate dielectric formed on the bottom gate is local to the bottom gate.

### Claim 22 (depends on 16)

The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the step of:
blanket depositing a gate dielectric material on the bottom gate and on at least a portion of the dielectric filling the cavities.

### Claim 23 (depends on 16)

The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the steps of:
forming a local gate dielectric on the bottom gate; and
forming a blanket gate dielectric on the local gate dielectric and at least a portion of the dielectric filling the cavities.

### Claim 24 (depends on 16)

The method of claim 16, wherein the step of forming the gate dielectric on the bottom gate comprises the step of:
oxidizing an upper portion of the bottom gate to form an oxide dielectric.