# US 8,785,910 B2 · Thin film transistor, display device including the same, and method of manufacturing the display device

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- Number: US 8,785,910 B2
- Document ID: US8785910B2
- Status: Granted
- Kind: B2
- Application number: 12/926,665
- Filed: 2010-12-02
- Published: 2011-06-09
- Granted: 2014-07-22
- Earliest claimed: 2009-12-04
- Assignees: Samsung Display Co., Ltd.
- Applicants: Jong-Hyun Park; Chun-Gi You; Sun Park; Jin-Hee Kang; Yul-Kyu Lee
- Inventors: Jong-Hyun Park; Chun-Gi You; Sun Park; Jin-Hee Kang; Yul-Kyu Lee
- Web page: https://patentgrep.com/patent/US8785910B2

## CPC

- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 62/40: Crystalline structures
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/0227: {using structural arrangements to control crystal growth, e.g. placement of grain filters}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A thin film transistor, a display device including the same, and a method of manufacturing the display device, the thin film transistor including a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor layer on the gate insulating layer; and source/drain electrodes electrically connected with the semiconductor layer, wherein the gate electrode has a thickness of about 500 Å to about 1500 Å and the gate insulating layer has a thickness of about 1600 Å to about 2500 Å.

## Claims

### Claim 1

A thin film transistor, comprising:
a substrate;
a gate electrode on the substrate;
a gate insulating layer on the gate electrode;
a semiconductor layer on the gate insulating layer; and
source/drain electrodes electrically connected with the semiconductor layer,
wherein:
the gate electrode has a thickness of about 500 Å to about 1500 Å and the gate insulating layer has a thickness of about 1600 Å to about 2500 Å,
the semiconductor layer has primary grain boundaries, and
a distance between the primary grain boundaries is about 2.75 μm to about 3 μm.

### Claim 2

A display device, comprising:
a substrate having a first region and a second region;
a gate electrode on each of the first region and second region of the substrate, respectively;
a gate insulating layer on the gate electrode;
semiconductor layers on the gate insulating layer in the first region and second regions of the substrate, respectively; and
source/drain electrodes electrically connected with the semiconductor layers on the first region and the second region of the substrate, respectively,
wherein:
the gate electrode has a thickness of about 500 Å to about 1500 Å and the gate insulating layer has a thickness of about 1600 Å to about 2500 Å,
each of the semiconductor layers has a primary grain boundary, and
a distance between the primary grain boundaries of the respective semiconductor layers is about 2.75 μm to about 3 μm.

### Claim 3 (depends on 2)

The display device as claimed in claim 2, further comprising a gate line electrically connected with at least one gate electrode, the gate line being on one of the semiconductor layers corresponding to the at least one gate electrode.

### Claim 4 (depends on 2)

The display device as claimed in claim 2, further comprising:
a passivation layer on the substrate including the source/drain electrodes thereon; and
a gate line on the passivation layer, the gate line being electrically connected with the gate electrode of the first region through contact holes in the passivation layer and the gate insulating layer on the first region.

### Claim 5 (depends on 2)

The display device as claimed in claim 2, further comprising:
a passivation layer on the substrate including the source/drain electrodes; and
a connection member on the passivation layer, the connection member being electrically connected with the gate electrode on the second region through contact holes in the passivation layer and the gate insulating layer.

### Claim 6 (depends on 5)

The display device as claimed in claim 5, wherein the connection member is electrically connected with the drain electrode on the first region through a contact hole in the passivation layer.

### Claim 7 (depends on 5)

The display device as claimed in claim 5, further comprising a contact member on the passivation layer, the contact member being electrically connected with the drain electrode on the second region through contact holes in the passivation layer.

### Claim 8 (depends on 7)

The display device as claimed in claim 7, further comprising a pixel electrode on the passivation layer, the pixel electrode being electrically connected with the contact member.

### Claim 9

A method of manufacturing a display device, the method comprising:
providing a substrate including a first region and a second region;
forming gate electrodes on the first region and second region of the substrate, respectively;
forming a gate insulating layer on the gate electrodes;
forming semiconductor layers on the gate insulating layer on the first region and second region of the substrate, respectively;
forming source/drain regions on certain regions of the semiconductor layers on the first region and second region of the substrate, respectively; and
forming source/drain electrodes in the first region and second region of the substrate, respectively, the source/drain electrodes being electrically connected with the semiconductor layers,
wherein:
the gate electrodes have a thickness of about 500 Å to about 1500 Å and the gate insulating layer has a thickness of about 1600 Å to about 2500 Å,
each of the semiconductor layers has a primary grain boundary, and
a distance between the primary grain boundaries of the respective semiconductor layers is about 2.75 μm to about 3 μm.

### Claim 10 (depends on 9)

The method as claimed in claim 9, wherein forming the semiconductor layer includes crystallization through sequential lateral solidification (SLS).

### Claim 11 (depends on 10)

The method as claimed in claim 10, wherein the SLS is performed using a mask having regions through which a laser beam penetrates.

### Claim 12 (depends on 11)

The method as claimed in claim 11, wherein:
the regions through which the laser beam penetrates have a length of about 4.5 μm to about 5.0 μm, and
a distance between the regions through which the laser beam penetrates is about 1.0 μm to about 1.5 μm.

### Claim 13 (depends on 9)

The method as claimed in claim 9, wherein forming the semiconductor layers includes:
forming an amorphous silicon (a-Si) layer on the gate insulating layer, and
performing an SLS process on the a-Si layer.