# US 8,785,909 B2 · Non-planar semiconductor device having channel region with low band-gap cladding layer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,785,909 B2
- Document ID: US8785909B2
- Status: Granted
- Kind: B2
- Application number: 13/629,148
- Filed: 2012-09-27
- Published: 2014-03-27
- Granted: 2014-07-22
- Earliest claimed: 2012-09-27
- Assignees: Intel Corporation
- Applicants: Marko Radosavljevic; Gilbert Dewey; Benjamin Chu-Kung; Dipanjan Basu; Sanaz K. Gardner; Satyarth Suri; Ravi Pillarisetty; Niloy Mukherjee; Han Wui Then; Robert S. Chau
- Inventors: Marko Radosavljevic; Gilbert Dewey; Benjamin Chu-Kung; Dipanjan Basu; Sanaz K. Gardner; Satyarth Suri; Ravi Pillarisetty; Niloy Mukherjee; Han Wui Then; Robert S. Chau
- Web page: https://patentgrep.com/patent/US8785909B2

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/123: {comprising junctions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/82: Heterojunctions
- H10D 62/852: being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP
- H10D 64/01: Manufacture or treatment
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Non-planar semiconductor devices having channel regions with low band-gap cladding layers are described. For example, a semiconductor device includes a vertical arrangement of a plurality of nanowires disposed above a substrate. Each nanowire includes an inner region having a first band gap and an outer cladding layer surrounding the inner region. The cladding layer has a second, lower band gap. A gate stack is disposed on and completely surrounds the channel region of each of the nanowires. The gate stack includes a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the channel regions of the nanowires.

## Claims

### Claim 1

A semiconductor device, comprising:
a vertical arrangement of a plurality of nanowires disposed above a substrate, each nanowire horizontally oriented with respect to the substrate and each nanowire comprising an inner region having a first band gap and an outer cladding layer surrounding the inner region, the cladding layer having a second, narrower band gap;
a gate stack disposed on and completely surrounding a channel region of each of the nanowires, the gate stack comprising a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer; and
source and drain regions disposed on either side of the channel regions of the nanowires.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the cladding layer comprises a material suitable to propagate a wave-function with low resistance.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the inner region of each channel region comprises a material suitable to substantially prevent current flow from source regions to drain regions.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein material pairs of the cladding layer and inner region are selected from the group consisting of InP/InGaAs, GaAs/AlGaAs and AlInSb/InSb.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the cladding layer is germanium-rich and the inner region is silicon-rich.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the cladding layer has a thickness suitable to propagate a substantial portion of a wave-function and to inhibit a significant portion of the wave-function from entering the inner region of each channel region.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the cladding layer has a thickness approximately in the range of 50-100 Angstroms.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the source and drain regions are formed within portions of each of the nanowires.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the source and drain regions of each nanowire are discrete relative to one another, the semiconductor device further comprising:
a conductive source contact surrounding each of the discrete source regions; and
a conductive drain contact surrounding each of the discrete drain regions.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the gate dielectric layer is a high-k gate dielectric layer, and the gate electrode is a metal gate electrode.

### Claim 11

A semiconductor device, comprising:
a hetero-structure disposed above a substrate and comprising a three-dimensional semiconductor body with a channel region comprising an inner region having a first band gap and an outer cladding layer at least partially surrounding the inner region, the cladding layer having a second, narrower band gap;
a gate stack disposed on and at least partially surrounding the channel region, the gate stack comprising a gate dielectric layer disposed on the cladding layer and a gate electrode disposed on the gate dielectric layer, wherein the cladding layer only partially surrounds the inner region of the channel region, and the gate stack only partially surrounds the channel region; and
source and drain regions disposed in the three-dimensional semiconductor body, on either side of channel region.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the cladding layer comprises a material suitable to propagate a wave-function with low resistance.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the inner region of the channel region comprises a material suitable to substantially prevent current flow from source region to drain region.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein material pairs of the cladding layer and inner region are selected from the group consisting of InP/InGaAs, GaAs/AlGaAs and AlInSb/InSb.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the cladding layer is germanium-rich and the inner region is silicon-rich.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein the cladding layer has a thickness suitable to propagate a substantial portion of a wave-function and to inhibit a significant portion of the wave-function from entering the inner region of the channel region.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the cladding layer has a thickness approximately in the range of 50-100 Angstroms.

### Claim 18 (depends on 11)

The semiconductor device of claim 11, wherein the gate dielectric layer is a high-k gate dielectric layer, and the gate electrode is a metal gate electrode.

### Claim 19

A semiconductor structure, comprising:
a first semiconductor device, comprising:
a first vertical arrangement of a plurality of nanowires disposed above a substrate, each nanowire comprising an inner region having a first band gap and an outer cladding layer surrounding the inner region, the cladding layer having a second, narrower band gap;
a first gate stack disposed on and completely surrounding a channel region of each of the nanowires, the first gate stack comprising a gate dielectric layer disposed on and surrounding the cladding layer and a gate electrode disposed on the gate dielectric layer; and
source and drain regions disposed on either side of the channel regions of the nanowires of the first vertical arrangement of the plurality of nanowires; and
a second semiconductor device, comprising:
a second vertical arrangement of a plurality of nanowires disposed above the substrate;
a second gate stack disposed on and completely surrounding a channel region of each of the nanowires, the second gate stack comprising a gate dielectric layer and a gate electrode disposed on the gate dielectric layer; and
source and drain regions disposed on either side of the channel regions of the nanowires of the second vertical arrangement of the plurality of nanowires.

### Claim 20 (depends on 19)

The semiconductor structure of claim 19, wherein the first semiconductor device is an NMOS device, and the second semiconductor device is a PMOS device.

### Claim 21 (depends on 20)

The semiconductor structure of claim 20, wherein the cladding layer and inner region form a group III-V material hetero-junction.

### Claim 22 (depends on 19)

The semiconductor structure of claim 19, wherein each nanowire of the second semiconductor device comprises a second inner region having a first band gap and a second outer cladding layer surrounding the second inner region, the second cladding layer having a second, narrower band gap.

### Claim 23 (depends on 22)

The semiconductor structure of claim 22, wherein the cladding layer and the second cladding layer each comprises a material suitable to propagate a wave-function with low resistance.

### Claim 24 (depends on 23)

The semiconductor structure of claim 23, wherein the inner region and the second inner region each comprises a material suitable to substantially prevent current flow from respective source regions to drain regions.

### Claim 25 (depends on 22)

The semiconductor structure of claim 22, wherein material pairs of the cladding layer and inner region are selected from the group consisting of InGaAs/InP, GaAs/AlGaAs and InSb/AlInSb, and wherein the second cladding layer is germanium-rich and the second inner region is silicon-rich.

### Claim 26 (depends on 22)

The semiconductor structure of claim 22, wherein each of the cladding layer and the second cladding layer has a thickness suitable to propagate a substantial portion of a wave-function and to inhibit a significant portion of the wave-function from entering the inner region and second inner region, respectively.

### Claim 27 (depends on 26)

The semiconductor structure of claim 26, wherein each of the cladding layer and the second cladding layer has a thickness approximately in the range of 50-100 Angstroms.

### Claim 28 (depends on 19)

The semiconductor structure of claim 19, wherein the gate dielectric layer of the first gate stack is a high-k gate dielectric layer, and the gate electrode of the first gate stack is an N-type metal gate electrode, and wherein the gate dielectric layer of the second gate stack is a high-k gate dielectric layer, and the gate electrode of the second gate stack is a P-type metal gate electrode.

### Claim 29

A semiconductor device, comprising:
a hetero-structure disposed above a substrate and comprising a three-dimensional semiconductor body with a channel region comprising an inner region having a first band gap and an outer cladding layer at least partially surrounding the inner region, the cladding layer having a second, narrower band gap, the three-dimensional semiconductor body horizontally oriented with respect to the substrate;
a gate stack disposed on and at least partially surrounding the channel region, the gate stack comprising a gate dielectric layer disposed on the cladding layer and a gate electrode disposed on the gate dielectric layer, wherein the cladding layer completely surrounds the inner region of the channel region, and the gate stack completely surrounds the channel region; and
source and drain regions disposed in the three-dimensional semiconductor body, on either side of channel region.

### Claim 30 (depends on 29)

The semiconductor device of claim 29, wherein material pairs of the cladding layer and inner region are selected from the group consisting of InP/InGaAs, GaAs/AlGaAs and AlInSb/InSb.

### Claim 31 (depends on 29)

The semiconductor device of claim 29, wherein the cladding layer is germanium-rich and the inner region is silicon-rich.