# US 8,785,903 B2 · Memory cell array and variable resistive memory device including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,785,903 B2 - Document ID: US8785903B2 - Status: Granted - Kind: B2 - Application number: 13/601,778 - Filed: 2012-08-31 - Published: 2013-11-28 - Granted: 2014-07-22 - Earliest claimed: 2012-05-24 - Assignees: SK hynix Inc. - Applicants: Sung Cheoul Kim; Kang Sik Choi - Inventors: Sung Cheoul Kim; Kang Sik Choi - Web page: https://patentgrep.com/patent/US8785903B2 ## CPC - H10B 63/34: {of the vertical channel field-effect transistor type} - H10B 61/22: {of the field-effect transistor [FET] type} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A memory cell array and a resistive variable memory device including the memory cell array are provided. The memory cell array includes a memory group. The memory cell array includes a pair of word lines, an inter-pattern insulating layer interposed between the pair of word lines, and a plurality of active pillars, each having one side contacted with the inter-pattern insulating layer and other sides surrounded by the word line. ## Claims ### Claim 1 A memory cell array, comprising: a pair of word lines; an inter-pattern insulating layer interposed between the pair of word lines; and a plurality of active pillars, each having one side contacted with the inter-pattern insulating layer and other sides surrounded by the word line. ### Claim 2 (depends on 1) The memory cell array of claim 1, further comprising: a plurality of memory groups, each including a plurality of the pairs of word lines and the plurality of active pillars arranged in a matrix, wherein the plurality of memory groups is arranged in a direction parallel to each other with a predetermined gap. ### Claim 3 (depends on 2) The memory cell array of claim 2, wherein the active pillar has a rectangular pillar shape. ### Claim 4 (depends on 3) The memory cell array of claim 3, wherein the sides of the active pillar have a first line width which corresponds to a critical dimension. ### Claim 5 (depends on 4) The memory cell array of claim 4, wherein the plurality of active pillars surrounded by each of the pair of word lines are spaced from each other by a distance corresponding to ½ of the first line width. ### Claim 6 (depends on 4) The memory cell array of claim 4, wherein a line width of the inter-pattern insulating layer arranged between the pair of word lines corresponds ½ of the first line width. ### Claim 7 (depends on 4) The memory cell array of claim 4, wherein the plurality of memory groups is separated from each other by a predetermined distance corresponding to ½ of the first line width. ### Claim 8 A memory cell array, comprising: a first memory group including a first word line, a second word line adjacent to the first word line and extending parallel to the first word line, a first inter-pattern insulating layer interposed between the first and second word lines, a plurality of first active pillars arranged between the first word line and the first inter-pattern insulating layer in a first rule, and a plurality of second active pillars formed between the second word line and the first inter-pattern insulating layer in the first rule to correspond to the plurality of first active pillars; and a second memory group including a third word line adjacent to the second word line and extending parallel to the second word line, a fourth word line adjacent to the third word line and extending parallel to the third word line, a second inter-pattern insulating layer interposed between the third and fourth word lines, a plurality of third active pillars arranged between the third word line and the second inter-pattern insulating layer in the first rule, and a plurality of fourth active pillars formed between the fourth word line and the second inter-pattern insulating layer in the first rule to correspond to the plurality of third active pillars. ### Claim 9 (depends on 8) The memory cell array of claim 8, wherein a size of contact between one of the pluralities of the first and second active pillars and the first inter-pattern insulating layer or a size of contact between one of the pluralities of the third and fourth active pillars and the second inter-pattern insulating layer corresponds to a first length. ### Claim 10 (depends on 9) The memory cell array of claim 9, wherein the first to fourth word lines are spaced from each other by a distance corresponding to ½ of the first length. ### Claim 11 (depends on 8) The memory cell array of claim 8, wherein one side of each of the pluralities of the first and second active pillars is in contact with the first inter-pattern insulating layer and remaining other sides are surrounded by the first or second word line. ### Claim 12 (depends on 8) The memory cell array of claim 8, wherein one side of each of the pluralities of the third and fourth active pillars is in contact with the second inter-pattern insulating layer and remaining other sides are surrounded by the third or fourth word line. ### Claim 13 A variable resistive memory device, comprising: a first word line; a second word line, arranged in a direction parallel to the first word line, and spaced from the first word line by a first length corresponding to a half of critical dimension; an inter-pattern insulating layer between the first and second word lines; a plurality of first active pillars surrounded by the first word line and the inter-pattern insulating layer, and arranged at intervals of the first length; a plurality of second active pillars surrounded by the second word line and the inter-pattern insulating layer, and arranged at intervals of the first length to correspond to the plurality of first active pillars; and a plurality of variable resistive bodies arranged on the pluralities of the first and second active pillars and electrically connected to the first and second active pillars. ### Claim 14 (depends on 13) The variable resistive memory device of claim 13, wherein the pluralities of first and second active pillars are configured that one side of the pluralities of first and second active pillars is in contact with the inter-pattern insulating layer, and remaining three sides of the pluralities of first and second active pillars are surrounded by the first or second word line. ### Claim 15 (depends on 14) The variable resistive memory device of claim 14, wherein each of the pluralities of first and second active pillars has a rectangular pillar shape, the active pillars are configured that one sides of the pluralities of first and second active pillars are in contact with the inter-pattern insulating layer, and remaining three sides of the pluralities of first and second active pillars are surrounded by the first or second word line. ### Claim 16 (depends on 13) The variable resistive memory device of claim 13, wherein the first and second word lines are formed to have heights lower than the pluralities of first and second active pillars. ### Claim 17 (depends on 13) The variable resistive memory device of claim 13, further comprising: a third word line adjacent to the second word line and arranged parallel to the second word line; a fourth word line adjacent to the third word line and arranged parallel to the third word line; an additional inter-pattern insulating layer between the third and fourth word lines; a plurality of third active pillars arranged between the third word line and the additional inter-pattern insulating layer in a distance of ½ of the first length; and a plurality of fourth active pillars formed between the fourth word line and the additional inter-pattern insulating layer in the distance of ½ of the first length to correspond to the plurality of third active pillars. ### Claim 18 (depends on 17) The variable resistive memory device of claim 17, further comprising variable resistive bodies formed on the pluralities of the third and fourth active pillars. ### Claim 19 (depends on 18) The variable resistive memory device of claim 18, further comprising drains arranged between the pluralities of first to fourth active pillars and the variable resistive bodies. ### Claim 20 (depends on 19) The variable resistive memory device of claim 19, wherein the semiconductor substrate further includes a common source electrically connected to the pluralities of first to fourth active pillars.